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sdram_test
- FPGA测试程序，使用XC3S250E对SDRAM进行读写的测试程序，SDRAM使用的是HY57V281620， 大小为128M。-FPGA test procedure, the use of XC3S250E SDRAM read and write on the test procedure, SDRAM using HY57V281620, size of 128M.
sdram_test
- FPGA开发入门实验，一个SOPC开发实例——流水灯实验，希望对对学者能有所帮助。-Introduction to FPGA development experiment, an example of SOPC development- light water experiment, in the hope that scholars will be helpful.
sdram_test
- sdram，dsp5509的外部ram 测试，学习和了解硬件结构-sdram，dsp5509
SDRAM_Test
- DSP6713向SDRAM写数据的源程序例程-DSP SDRAM TEST
SDRAM_TEST
- SDRAM控制代码，已经在开发板上测试通过。-SDRAM control code has been tested on the development board.
SDRAM_TEST
- 用Verilog硬件描述语言驱动SDRAM，内有完整可实现源代码，且还有现象说明-With the Verilog hardware descr iption language driven SDRAM, can be realized within the complete source code, and there is the phenomenon described
sdram_test
- 自己实现的一个基于SOPC架构的SDRAM模块-Own implementation of an architecture based on SOPC SDRAM module
SDRAM_test
- 基于DSP6713，对外挂的SDRAM进行读写测试，可以用做对DSP的EMIF外设操用的参考。-Based on the DSP6713, read and write test plug on SDRAM, can be used on the DSP EMIF peripheral fuck with reference.
C6416
- 这些文件夹为6416CPU板测试程序 Flash_test：flash烧写 Sdram_test：sdram测试 timerint：led_d5闪烁测试-These folders to 6416CPU board test program Flash_test: flash programmer Sdram_test: sdram test timerint: led_d5 flash test
SDRAM_Test
- SDRAM Verilog HDL 测试代码，含有时序约束。-SDRAM Verilog HDL test code contains timing constraints.
SDRAM_test
- DSP6713的存储器测试程序，包括FPGA的接口程序，DSP与FPGA协同工作。-DSP6713 memory test program, including the FPGA interface program, DSP and FPGA to work together.
sdram_demo_de2_115
- 适用于DE2 115开发板的SDRAM测试代码，基于黑金开发板改编，可以直接下载到DE2 115上面。内部有所有代码解释-FPGA SDRAM_TEST DE2 115
sdram_test
- 这个是经典的sdram的驱动代码，可能你需要留意下具体的芯片型号，我在里面都有介绍，已调可用，并且真的是非常经典-This is a classic sdram driver code, you may need to pay attention to the specific chip model, which I have introduced in the modulated available and really is very classic
SDRAM_TEST
- SDRAM控制程序提供SDRAM数据地址的读写控制-SDRAM WRITE/READcontrol module
sdram_test
- 在vivado中用于测试SDRAM，DDR3学习比较有帮助-the testbench for ddr3
11_sdram_test
- module sdram_test( input clk_50m, input reset_n, //sdram control output S_CLK, //sdram clock output S_CKE, //sdram clock enable output S_NCS, //sdram chip select output S_NWE, //sdram write enable output S_NC
sdram_test
- 针对黑金AX309开发板的SDRAM控制程序。基于ISE 14.7，语言为Verilog。实测可用。(For the black gold AX309 development board SDRAM control program. Based on ISE 14.7, the language is Verilog. Measured available.)