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这是我在ISP编程实验中独立编写的采用结构化描述的一个七人表决器，通过独特的3次映射一位全加器的方法从而实现七人表决器的功能，与网络上任何其他的七人表决器源码决无雷同。-This is my ISP programming in an independent experiment using a structured, prepared as described in a seven-member voting machine, through a unique 3 times a full a
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一位全加器源码实现了MAX及其一系列器件实现全加的功能-A full adder and its source code to achieve the MAX series of devices to achieve the functions of the All-Canadian
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一位全加器的VHDL源码与TEST BENCH.XILINX下通过-A full adder and the VHDL source code through TEST BENCH.XILINX
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this vhdl source code for multiplexer,half adder,full adder,counter etc. for using in ACTIVE HDL and other vlsi softwares.-this is vhdl source code for multiplexer,half adder,full adder,counter etc. for using in ACTIVE HDL and other vlsi softwares.
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