搜索资源列表
Spartan-3E.rar
- Spartan-3E 中文介绍（包括图解、功能介绍、使用方法、锁管脚等）,Spartan-3E Starter Kit Board User Guide
Xilinx_sparten3E_communication
- 在Xilinx Spartan-3E的开发板中，实现键盘和VGA显示器的通信的源代码，与大家分享：,In the Xilinx Spartan-3E development board, the realization of the keyboard and VGA display the source code of communication to share with you:
lcd_driver_4bit
- it is a 4-bit lcd driver written in verilog .it will work on spartan 3 xilini devices.
VGA
- 基于Xilinx SPARTAN-3E开发板 的VGA实验代码，VHDL编写，非常适合初学者学习FPGA实现VGA控制-Based on Xilinx SPARTAN-3E development board VGA test code, VHDL written, very suitable for beginners to learn to achieve VGA control FPGA
using_the_block_RAM_in_Spartan-3_FPGA
- Spartan-3 系列 FPGA 中的 Block RAM 的使用-using the block RAM in Spartan-3 FPGA
RS232.VHDL
- RS232 Communication function in VHDL for Spartan 3E
SPARTAN-3E
- SPARTAN-3E的说明文档,详解的描述了SPARTAN-3E的使用方法-SPARTAN-3E descr iption of documents, detailed descr iption of the SPARTAN-3E use
pong
- Pong is a mixed schematic, VHDL, Verilog project featuring the PS2 and VGA monitor connections of the Xilinx\Digilent Spartan-3 demo board.
Rs232sourcecode
- Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested in FPGA Spartan 3 Included files for testing at FPGA - Scan4digit .vhd - to display at 7 sgement display - D4to7 .vhd - Convert HEX decimal to
Avt3S400A_Eval_MB_parallel_flash_v10_1_01
- FPGA 并行NOR FLash的操作相关，很实用的，基于Xilinx SPartan-3 -FPGA parallel operation of NOR FLash related, it is practical, based on the Xilinx SPartan-3
Spartan-3_NeuralNetwork_3-layer_feedforward_backp
- The aim of this project is the design and implementation of a system simulating a NN in the Spartan-3 Starter Board of Xilinx. The NN will be a 3-layer feedforward backpropagation.- The aim of this project is the design and implementation of
rafal2
- VHDL project for FPGA SPartan 3 using IseWebpack 10.1. This is an implemetation of FSM for testing 7 segment with dot point 4 digit LED display.
wtut_sc
- DCM includes a clock delay locked loop used to minimize clock skew for Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X devices. DCM synchronizes the clock signal at the feedback clock input (CLKFB) to the clock signal at the input clock
EDK_81
- 视频文件 EDK_81,xilinx spartan-3-EDK_81,xilinx spartan-3
sl361_board_files
- spartan-3开发板原理图，好东西大家共享-spartan-3 development board schematics, share good things
SP305-Spartan-3
- SP305 Spartan-3 Development Platform User Guide
Spartan-3-FPGA-Family-Data-Sheet
- Spartan-3 FPGA Family Data Sheet
Spartan-3-Complete-data-sheet
- Spartan-3 Complete data sheet
Spartan-3-FPGA-FamilyPinout-Descriptions-data
- Spartan-3 FPGA FamilyPinout Descr iptions data
ug331 Spartan-3 系列 FPGA 中文用户指南
- 官方手册ug331的中文版 本用户指南为客户使用 Spartan?-3 FPGA 系列各平台 （Spartan-3、Spartan-3E、 Spartan-3A、Spartan-3AN 和 Spartan-3A DSP FPGA 平台）的架构功能提供指导。本文 综合了各平台的技术文档，以便于了解其中异同，同时减少多种资料来源的内容重复。这些平台是新设计的补充解决方案。(ug331 Spartan-3 Generation FPGA User Guide)