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spi_boot-rel_3_2_rev_C.tar
- spi bootloader详细资料，里面包含C代码和VHDL代码以及testbench以及相关的说明文档，有兴趣的朋友可以下来看看。
spi_verilog
- SPI协议Verilog HDL程序，内含testbench 文件
MinWinsockSpi
- verilog ADPLL file with testbench
SPI_FireWall
- verilog spi file with testbench
wince+spi
- verilog vcspi file with testbench
spi2-testbench
- test bench for spi communication
SpiMaster
- This a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate-This is a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile an
maxII_spi
- MAXII SPI interface with testbench
spi_master
- 用VHDL编写的一个SPI主机程序，SPI模块采用最常用的模式0方式（即CPOL=0,CPHA=0）通信。文件内含测试文档，已在Modelsim6.5上测试通过，可在FPGA上直接调用。-A SPI Master code edited by VHDL language,the SPI modul use 0 MODE(i.e CPOL=0,CPHA=0)to communicate with the SPI Slave.and there is a testbench in the file
spi_vmm1.2
- VMM1.2的SPI示例代码，介绍各个验证组件的功能和用法。Verilog编写，使用VCS仿真-The example SPI testbench code of the VMM1.2
SPI-Core_nguyen
- SPI Master Core HDL: VHDL 93 Compatibility: all FPGAs, CPLDs parameterization: - variable data width - Phase/polarity configurable - selectable buffer depth - serial clock devision due to system clock package usage: IEEE
ADC_AD7490
- THIS PROJECT IMPLEMENTED ON VITERX 4 FPGA and THE COMPLETE SOURCE FILES testbench, design file UCF file are there and THIS ADC is maily configured with SPI protocol interface SPI CLK,SPI DATA, SPI LE, the SPEED OF OPERATION OF SPI CLK is 10 MHZ
SPI-master-P-tb
- SPI master VHDL realisation Also contains TestBench
spi
- It is a Verilog code for SPI master. It includes source code and a testbench to test the functionality.-It is a Verilog code for SPI master. It includes source code and a testbench to test the functionality.
spi slave程序
- spi slave的verilog程序，有测试平台testbench程序，实现fpga作为salve的功能(spi slave verilog program)
W25Q80NE verilog Model
- SPI FLASH官方仿真模型方便modelsim testbench调试仿真(Official simulation model facilitates debugging and simulation)
SPI接口Verilog实现
- 里面有主机发送模块和从机接收模块。主机发送32位16进制数（一位一位发送），工作在模式0。压缩文件内代码可直接运行，另附上testbench文件可以进行modelsim仿真。此代码根据论坛里一位大哥的代码改编，后来找不到是谁了。。。使用状态机编写主机的发送模块，由于项目仅仅需要主机发送所以从机的接收模块没有写成32位的，但是代码风格清晰，可以直接修改，复写率极高且非常好理解！