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用FPGA实现SRAM读写控制的Verilog代码
- 用FPGA实现SRAM读写控制的Verilog代码-SRAM FPGA implementation using Verilog code to read and write control
SRAM
- stm32f103zet6,通过stm32的fsmc来对sram的控制，实现数据读写-stm32f103zet6, through stm32 of fsmc to the control of sram, read and write data
Verilog_SRAM.rar
- 使用Verilog写的SRAM的控制程序，仅供参考！,The use of the SRAM write Verilog the control procedures, for reference purposes only!
FIFO
- verilog编写的读写fifo的源码，包括sram的读写控制-verilog source code written to read and write fifo, including the sram to read and write control
USB_FPGA_FOR_SRAM-control
- 此程序完成PC上位机通过USB与板上SRAM进行的数据传输交换，有CY7C68013A的SALVE_FIFO的完整固件及FPGA的SRAM驱动程序，并已调通可用了。-This process is complete PC via USB and PC-board SRAM for data transfer exchange, complete with CY7C68013A of SALVE_FIFO of SRAM FPGA firmware and drivers, and has bee
Verilog-SRAM
- 用verilog hdl语言编写的fpga与片外sram 的读写控制-With the verilog hdl language fpga sram chip with read and write control
sram
- 用FPGA 控制sram读写程序的小程序，-fpga control precedure
fpga_sram
- Altera cyclone ep1c6对sram idt71系列的读写时序控制-Altera cyclone ep1c6 of sram idt71 series of read and write timing control
C20_sram_vga
- FPGA应用如sd卡控制，led控制，vga音频控制-Sd card FPGA applications such as control, led control, vga audio control
sram216
- SRAM IS61LVC12824,读写控制程序，用CPLD 95216设计-SRAM IS61LVC12824, read and write control procedures, with the design of CPLD 95216
PWM
- verilog pwm to control servo motor on quartus, with microprocessor generated from sopc and connected with sram-verilog pwm to control servo motor on quartus
sram
- 对常用的sram完成读写控制，可以根据具体地址增加参数，非常灵活-Commonly used to read and write sram to complete control, can be increased in accordance with the specific parameters of address, a very flexible
SRAM_Controller
- Altera University Program的Avalon总线IP核，SRAM控制代码，可以解压后直接挂载在Avalon总线上 -Altera University Program of the Avalon bus IP core, SRAM control code can be directly mounted after decompression in the Avalon bus
keylcdpwm-sram
- 利用DSP 2812,通过键盘控制液晶12864的显示.-The use of DSP 2812, through the keyboard control the liquid crystal display 12864.
yuyincaiji
- 语音采集与回放系统源代码：1.为了使读音数据存储的时间更长，速度更快，选用了256K*16Bit的SRAM；2.为了减少单片机的控制复杂度，使用了FPGA来控制SRAM的读写操作，节约了不少单片机的I/O资源；3.为了以后的高速数据存储，本设计中加入了fifo,其位宽及深度可在程序中自由设置，方便灵活。-Speech acquisition and playback system source code: 1. In order to make pronunciation longer data
sram_saa1117verilog
- 图像采集、存储控制verilog源代码，fpga控制SAA1117,采集数据存储到sram，仿真编译测试都能通过-Image acquisition, storage, control verilog source code, fpga control SAA1117, collecting data to sram, simulation tests can be compiled by
sram
- 基于FPGA的SRAM控制程序，里面附加了在线逻辑分析功能的程序，调试时相当的方便-SRAM-based FPGA-control program, which added an online feature of the program logic analysis, debugging very convenient when
SRAM_Control
- VHDL Code for SRAM Control (Synthesized with Synplify-Pro, Active-HDL Simulation)
SRAM
- FPGA控制SRAM的VERILOG源码-The VERILOG source code control SRAM FPGA
SRAM
- This is SRAM control application source code for ST32F103 ST MCU.