设计ip协议的vhdl实现，对作通讯硬件的朋友因该有所帮助-design ip agreement vhdl realization of communications hardware for a friend because of the help

VHDL IP Stack: This IP stack for an FPGA is a complex design because of the number of layers and the complexity of each that is required. It is limited to 10Mb/s operation and is designed for a full duplex switched network. It implements the lower la