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Pld_lab4
- stop watch in vhdl using MAXII development board.
stopwatch
- 数字秒表的VHDL代码。当设计文件加载到目标器件后，设计的数字秒表从00-00-00开始计秒。，直到按下停止按键（按键开关S2）。数码管停止计秒。按下开始按键（按键开关S1），数码管继续进行计秒。按下复位按键（核心板上复位键）秒表从00-00-00重新开始计秒。-The VHDL code for digital stopwatch. When the design document loaded into the target device, the designed digital stop
Stopwatch
- Stop-watch for FPGA on 7 segment display
EDA-experiments-based-on-VHDL
- 上传的文件包括E有关EDA实验的程序，比如FIFO，秒表，数字钟，七段数码管，状态机检测序列-The files uploaded contain some source code of EDA experiments based on VHDL, such as FIFO, digital clock, stop watch, digital tubes and sequential detector.
watchvhd
- WATCHVHD硬件描述语言(VHDL)是一个顶级的一个停表类型项目。-WATCHVHD is a top level VHDL type project of a Stop Watch.
VHDL Digital Clock
- A digital stop watch designed in VHDL
stopWatch
- 基于VHDL语言数字秒表的实现！使用模块化的设计，包含详细设计说明文档。可在DE2-115开发板上进行验证！-digital stop watch based on VHDL language