搜索资源列表
AdderSubtractor
- 4-Bit Adder Subtractor Verilog Code. (Complete project)
HA
- Verilog HDL for Half Adder, Full Subtractor, Half Subtractor and 2x4 decoder.
subtractor
- Verilog source code for full subtractor module build with predefined nor gates.
subtractor2
- Verilog full subtractor module and tests build with a half subtractor made with predefined nand gates.
subtractor3
- Verilog 3bit full subtractor module and tests build with predefined nor gates.
subtractor4
- Verilog half subtractor module and tests build with made with gates built with expression modules.
Simple_Verilog_Code_For_Beginner
- verilog code for beginner (adder, comparator, mux, or, and subtractor)
addersubtractor
- adder subtractor...this source is example to build adder and subtractor code in verilog (.v)
lab
- verilog语言设计同步加法器，异步减法器，16位计数器-adder verilog language design synchronous, asynchronous subtractor, 16-bit counter
addsub
- Verilog HDL: Adder/Subtractor
Verilog-fpga-cailiao
- 这是fpga板子自带的verilog程序，包含流水等 彩灯，加法器，减法器，等多个程序！-This is the verilog fpga board comes with the program, including water and other lights, adder, subtractor, and other programs!
module-hs
- half subtractor verilog code is written using verilog hardware descr iption language
add_ded_module
- 使用Verilog语言编写的4位加减法器，经验证能在FPGA开发板上实现。-Verilog4 bit adder-subtractor.
jianfa_sub
- 基于FPGA的减法器的verilog程序源代码-FPGA-based subtractor verilog source code
verilog-source-codes
- the attached programs are source codes of 4-bit ring counter, 16x1 mux, 8x3 priority encoder, 4x16 decoder, full subtractor using two half subtractors
accsub
- 简单的加法器减法器程序代码，Verilog HDL初学者学习可以使用-Simple adder subtractor code, Verilog HDL beginners can use