搜索资源列表
SystemVerilog_2nd.pdf
- System Verilog 验证设计。主要讲如何编写测试用例。设计数字电路比较经典的教程。-System Verilog design verification. Mainly about how to write test cases. Digital circuit design more classic tutorial.
SystemVerilogAssertions
- Srikanth Vijayaraghavan - A Practical Guide for SystemVerilog Assertions-Srikanth Vijayaraghavan- A Practical Guide for SystemVerilog Assertions
Verilog_VHDL
- Verilog——解决初学者疑惑：VHDL、Verilog，System+verilog比较.pdf-Comparison of VHDL, Verilog and SystemVerilog
Verilog_Gotchas_Part2.pdf
- This paper documents 38 gotchas when using the Verilog and SystemVerilog languages.
Writing-testbenches-using-SystemVerilog.pdf.tar.g
- systemverilog testing
Comparison
- VHDL，verilog and SystemVerilog的优缺点说明-Comparison of VHDL, Verilog and SystemVerilog.pdf
SystemVerilog
- System Verilog中英文资料大全（pdf文档）-System Verilog Sourcebooks of Chinese and English (pdf document)
UVM1.1应用指南及源代码分析_20111211版.pdf
- 该书用来介绍UVM的架构，语法，包含很多示例，适用于初学者(The book used to introduce the UVM architecture, syntax, including many examples, for beginners)
[IEEE]SystemVerilog.std.1800-2012.pdf
- [IEEE]SystemVerilog.std.1800-2012