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tsmc_018um_model
- tsmc 180nm cmos模型,可以应用于hspice等仿真软件-tsmc 180nm cmos model, which can be used in hspice.
SerDes
- 12.5 Gb/s半速率时钟数据恢复电路(CDR)的 设计及6.25Gb/s SerDes接收芯片的系统集成,设计工艺均为tsmc 0.189in CMOS工艺。-aspects:Design of Half-rate 1 2.5 Gb/s Clock Data Recovery (CDR)and Integration of 6.25Gb/s SerDes receiver.Both are realized in tsmc 0.1 89m CMOS process.
SCH
- DTMB GB20600-2006 terrestrial dig FPGA or CPLD reads the SD card IP tell us how to divide frequency f UMC 90nm design models. please re UMMC 90nm models. Please read the Bluetooth serial port via the pho scope FPGA code AG 0.35u