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uart
- VHDL编写的异步通信串行口设计用Quartus工具编译
nios_uart程序
- 该quartus的基于SOPC串口程序经过调试成功，对NIOS的初学者很有用。
uart
- Verilog实现串口收发数据，包括整个quartus工程-Verilog serial port to send and receive data, including the whole quartus project
uart
- uart的vhdl实现，包含完整quartus工程文件，相信会有较大帮助-uart vhdl quartus
UART
- 语言：verilog语言 功能：通过串口控制模块，实现FPGA与串口 通信。 仿真环境：modelsim 综合环境：quartus -Language: verilog language function: through the serial port control module, FPGA and serial communication. Simulation Environment: modelsim integrated environment: quartu
UART
- 使用Quartus ii软件，编程语言为Verilog语言，实现UART通信协议，FPGA的时钟信号为50MHz-Using the Quartus ii software, programming languages Verilog, UART communication protocol implementation, FPGA 50MHz clock signal
UART
- 實作UART 介面 4 byte 傳送 或 4 byte 接收 開發環鏡 quartus 且 附模擬檔-4 byte real interfaces for UART transmission or 4 byte receive loop mirror quartus and the development of simulation files attached
uart_read_send
- uart自收发的vhdl实现,包括quartus工程文件及modelsim仿真工程文件(调试通过)-uart vhdl from the transceiver to achieve, including the quartus project file and modelsim simulation project file (debugged)
uart
- uart IP CORE Verilog quartus-uart IP CORE Verilog quartusii
uart
- 基于VHDL语言的fpga uart 口通讯的源程序，经验证可用，开发环境Quartus -VHDL UART QUARTUS II
demo7-uart
- quartus 串口程序 可以通过开发板的串口对FPGA进行读写操作-the quartus serial program can development board through the serial port on the FPGA to read and write operations
uart
- uart串口通讯，波特率任意可调，采用vhdl语言编写，ise和quartus均可使用-uart serial communication baud rate of any adjustable
uart
- 一个在Quartus 12.0 Web版下做的Uart收发例子，具备基本的收发功能。-Uart transceivers example, with a in Quartus 12.0 Web version under the basic functions of the transceiver.
UART-VHDL-QUARTUS
- uart vhdl quartus for altera
uart
- quartus平台下实现串口IO收发功能模块。可以直接使用，有需要的参考一下。-The quartus platform to achieve the serial IO transceivers functional modules. Can be used directly, there is a need reference.
UART
- 基于quartus ii 11.0与nios ii 11.0 串口通信-Serial communication based on II quartus 11 and II NIOS 11
uart
- 本例程是用verilog硬件描述语言在quaryusII环境下开发的串口通信模块，分为发送模块，接受模块和波特率产生模块。-This routine is verilog hardware descr iption language development environment under quartus II serial communication module, divided into send module, receive module and baud rate generato
UART
- 用Verilog实现的全局异步接收发送机，在quartus平台测试成功。(Use Verilog implementation of global asynchronous receive transmitter in quartus platform test successfully)
uart程序_quartus_verilog
- 该程序实现uart串口收发数据，按照通信数据格式，代码编写规范，实现fpga中uart通信功能。(The program realizes the UART serial transceiver data, according to the communication data format, code specification, to achieve UART communication function in fpga.)
uart
- UART接口的基于FPGA芯片，用Verilog语言实现，在quartus上操作(UART interface is implemented by FPGA)