搜索资源列表
UART
- 内含有完整的UART代码，包括发送和接受，且有testbench，可以直接仿真调试-Contain complete UART code, including send and receive and there testbench, can directly Simulation debugging
UARTtransmitter
- UART Transmitter. VHDL code and its testbench.
uart-vhdl-testbench
- simple uart vhdl behavioural model (package) vhdl testbench example
UART
- 用VHDL编写实现的UART控制器源码，自带testbench，解压后用ISE打开工程文件即可。-Prepared with the VHDL source code to achieve the UART controller, bring their own testbench, after decompression project file can be opened with the ISE.
uart2bus_latest.tar
- 文档详尽、已验证的UART工程，含有testbench文件。采用VHDL、Verilog语言编写。-Detailed documentation, has proven UART works with testbench file. Using VHDL, Verilog language.
UART
- UART发送verilog源码，波特率115200，以及testbench源码-Send verilog source UART baud rate 115200, and testbench source
verilog
- 这是一个uart串口实现16550的实现，代码已测试过了。-This is a 16550 uart serial port, the code has been tested before.
uart_tb
- Uart testbench in SV
uart
- uart veilog源码 含有testbench-uart verilog
uart
- verilog实现UART收发源码 内有testbench-the UART transceiver Source for verilog implementation With testbench
uart_tb
- simple UART testbench code.inlucding
uart_tb
- Uart testbench in SV
RS422_UART
- RS422 串口通讯 （包括 testbench，虚拟RAM，数据收发，波特率生成，数据接收抗干扰）-RS422 UART testbench BaudGen
uart
- 这是一个串口通讯模块，从串口接收14个数据后用于计算并将计算结果从串口发送出去，里面包含testbench。-This is a serial communication module 14 the serial port to receive data used to calculate the results and sent the serial port, which contains the testbench.
uart
- Atmega 328 UART clone with testbench, cannot be synthesized to gates
Uart-Verilog
- verilog实现串口通讯，包括verilog代码和testbench代码-verilog serial communication, including the verilog code and testbench Code
UART-master
- UART通讯接口verilog代码实现，uart_tx子模块和uart_rx子模块，包含详细testbench-UART interface verilog code, uart_tx、uart_rx， testbench
apb_uart
- 带apb接口的uart,带testbench，测试过，可以使用(The uart module with apb interface)
uart
- 用Verilog实现FPGA的uart的串行通信功能，并附有testbench(The serial communication function of FPGA of UART is realized with Verilog, and Testbench is attached)
apb_uart_sv-pulpinov1
- SystemVerilog 写的APB总线接口的uart 代码，带testbench.(Uart code of APB bus interface written by SystemVerilog, with testbench.)