当前位置：
首页 资源下载
搜索资源 - uart vhdl testbench
搜索资源列表
-
2下载：
内含有完整的UART代码，包括发送和接受，且有testbench，可以直接仿真调试-Contain complete UART code, including send and receive and there testbench, can directly Simulation debugging
-
-
0下载：
UART Transmitter. VHDL code and its testbench.
-
-
0下载：
simple uart vhdl behavioural model (package)
vhdl testbench example
-
-
0下载：
用VHDL编写实现的UART控制器源码，自带testbench，解压后用ISE打开工程文件即可。-Prepared with the VHDL source code to achieve the UART controller, bring their own testbench, after decompression project file can be opened with the ISE.
-
-
0下载：
文档详尽、已验证的UART工程，含有testbench文件。采用VHDL、Verilog语言编写。-Detailed documentation, has proven UART works with testbench file. Using VHDL, Verilog language.
-
-
0下载：
UART VHDL sources with FIFO-UART VHDL sources with FIFO,baudrate,receiver,transmitter,register,testbench
-
