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Verilog_UDP
- 辛辛苦苦找到的UDP的资料，在verilog中UDP指的是用户定义的原语。比如说大家有时候会见到“primitive...table...endtable...endendprimitive”这样的代码段，在书上只能找到大概的解释。到网上查的话又老是跟TCP/IP的UDP冲突。所以特地搜集到了这个东西，希望能帮助大家解决“用户原语”相关的问题。-UDP hard to find the information in verilog in the UDP refers to the user-de
udp_ip__core_latest.tar
- udp/ip stack for just streaming the data over IP video or audio vhdl code to run in vhdl
auk_udpipmac-v3.3.0.tar
- The Altera(R) UDP/IP function implements a hardware solution for the transmission and reception of UDP/IP encapsulated network traffic.
angel_php
- Describe: VHDL Cookbook including many useful building blocks. Develop tools: VHDL | File size:4374KB | Downloads: 0 [TCP/IP Stack] back4.zip <ding_xinyi> upload at 2011-9-17 4:40:30 Describe: UDP java reference reliable transmission,
udp_ip_stack_latest.tar
- Udp-IP Stack for ethernet on fpga (vhdl descr iption)