搜索资源列表
uvm-1.0p1.tar
- Cadence 公司推出的高级验证语言，验证方法学开源-Cadence s introduction of an advanced verification languages, verification methodology open source
uvm-1.1d.tar
- UVM World 官方发布的UVM（通用验证方法学）的源代码，基于SystemVerilog，用于ASIC Verification。2013-03最新发布版本uvm-1.1d.tar.gz-The UVM World official release of the source code of the UVM (Universal Verification Methodology), based on SystemVerilog for ASIC Verification. 2013-03
uvm
- UVM验证平台的介绍，在验证方面效率由于systemverilog。-UVM verification platform introduced in verification efficiency due systemverilog.
uvm_switch_8
- 使用uvm验证环境搭建的testbench，主要验证switch的功能。可以学习uvm的简单功能-use uvm set up testbench ,the mainly focuse is verification swtich,you can learning uvm sample fucntion
uvm-1.1d
- uvm 源代码开发，基于此可以实现芯片验证加速和验证充分保证-uvm system verilog based code
UVM_Class_Reference_Manual_1.2
- UVM 1.2 类参考手册，UVM验证必备-UVM 1.2 class reference manual
UVM
- uvm验证方法学入门。step by step，适合IC验证人员入门-uvm verification methodology started. step by step, for IC verification personnel entry
uvm_lab_switch
- 利用最新的UVM验证方法学搭建完整的ASIC的验证平台。-UVM and svtb for ASIC verification
uvm_exp
- uvm验证平台简单环境搭建，来自于书《uvm1.1应用指南及源代码分析》，但书中代码无法直接运行，需要进行部分修改。-a simple uvm env
uvm_users_guide_1.2
- UVM验证方法学官方的文档 uvm_users_guide_1.2-uvm users guide 1.2
uvm-1.1
- 学习IC验证的好资料，包括UVM-1.1a和UVM-1.1d的全部工程example,适合IC验证基于UVM平台的初学者。-Learn good about IC verification, including all engineering of UVM-1.1a and UVM-1.1d, for beginners based on the UVM platform for IC verification.
UVM-Ver
- 关于UVM验证方法学的3篇文档，配合UVM-1.1实例，适合刚跨入IC验证领域的同学自学，内容详实，通俗易懂。-On the UVM verification method of the three documents, with UVM-1.1 example, just for the IC into the field of verification of self-learning, content is detailed, easy to understand.
uvm_users_guide_1.2
- uvm验证方法学用户参考手册或指导，非常有用，对IC验证工程师来说，UVM方法学是非常重要的- 46/5000 Uvm yànzhèng fāngfǎ xué yònghù cānkǎo shǒucè huò zhǐdǎo, fēicháng yǒuyòng, duì IC yànzhèng gōngchéngshī lái shuō,UVM fāngfǎ xué shì fēicháng zhòngyào de Uvm Validation Methodology User Ref
uart2bus_testbench_latest.tar
- uart2bus_testbench,uart测试平台，主要运用uvm验证方法学，对uart接口、systemverilog和uvm等ic开发和验证有一个初步了解和掌握。-Uart2bus_testbench, uart test platform, the main use of uvm validation methodology, uart interface, systemverilog and uvm ic development and verification have a pre
uvm-tutorial-for-candy-lovers-master
- 张强书所带代码和PDF,代码验证可用,好好学习(Zhang Qiangshu's code and PDF)
proj
- UVM验证平台，使用时直接解压即可。123456789999(UVM verification platform, direct unzip can be used.1234567899999)
uvm-1.1d.tar
- UVM验证平台需要的UVM库。最新版本为UVM1.1d。(The UVM library required by the UVM authentication platform.)
apb uvm验证testbench
- 一个apb的uvm验证uvc,可以寄经过简单修改，建立testbench，非常便利，需要在uvm验证环境中搭建uvm验证平台
uvm实战源码
- uvm实战教程源码，丰富的uvm demo testbench,可以学习uvm各个阶段的testbench搭建技巧，能学习到大量的uvm testbench搭建技能，比如factory和寄存器模型等重要机制，非常值得学习
UVM验证平台搭建
- 搭建uvm验证平台,通用验证平台结构和搭建流程介绍(How to build a common UVM verification platform?An easy and useful method is instroduced here.)