搜索资源列表
ref-ddr-sdram-verilog.zip
- sdram的verilog的源码实现,sdram verilog source code realizes
dual_RAM.rar
- actel fusion startkit FPGA开发板试验例程，可实现2k8的双口ram，实现数据存储，缓冲。包含verilog HDL 语言源码,actel fusion startkit FPGA development board test routines, can be realized 2k8' s dual-port ram, achieving data storage, buffer. Language source code contains the verilog
AMBA-Bus_Verilog_Model
- 该源码包是2.0版本的AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型，AHB总线上从设备RAM模型，参数定义。-This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_R
fifo的vhdl原代码
- 本文为verilog的源代码-In this paper, the source code for Verilog
profiles
- source code of counter,ram,lfsr etc
LIP2301CORE_Synthesisable-RAM
- Verilog Synthesisable RAM source code
ram_sp_ar_sw.v
- this is a verilog source code for Single Port RAM Synchronous Read/Write.
ram_sp_sr_sw.v
- this is a verilog source code for Single Port RAM Synchronous Read/Write.
ram_dp_sr_sw.v
- this is a verilog source code for Dual Port RAM Synchronous Read/Write.
一种arm7源码（Verilog）
- 一种arm7源码（verilog），arm7结构比较老了，不过用来初学还是不错的(A kind of ARM7 source code (Verilog))