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DDS
- FPGA中实现基于查找表方式（LUT）的DDS实现，可用在数字下变频和COSTAS锁相环中，Verilog编写，本人已经调通
costas的verilog程序
- costas的verilog程序，包含乘法器，DDS，鉴相器，环路滤波器等模块-costas the verilog program, including multipliers, DDS, phase detector, loop filter modules
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- 基于matlab和QuartusII开发的无线通信FPGA设计,内有(matlab代码,Verilog代码,缩略语表.doc)注释详细,代码数十个,总有一个是你喜欢的!-Matlab and QuartusII based on the development of wireless communications FPGA design, there are (matlab code, Verilog code abbreviations. Doc) Notes detail dozens of
costas_loop
- 集中式插入式帧同步发的verilog源代码-concentrative inserted frame sync
costas
- 载波同步，costas环，基于Verilog的载波同步环-Carrier synchronization, costas ring, based on Verilog carrier synchronization ring
COSTAS_LOOP
- 用verilog编写的科斯塔斯环，希望有帮助-Costas loop written in verilog helpful
costasc_verilog
- 实现costas环，用verilog语言实现，缺少乘法器，可以自己添加-Realization of Costas ring, with the Verilog language implementation, the lack of multiplier, you can add their own.
costas-loop-in-ISE
- ISE软件中实现costas环的方案，使用语言为verilog。文件为word形式，不含有源代码，只包含实现过程及注意事项。-ISE COSTAS LOOP
COSTAS环载波同步
- how to come ture a costas loop in FPGA with verilog,it is very useful on project