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MCU-counter
- 用verilog实现单片机计数器 用verilog实现单片机计数器-MCU with verilog counter with MCU counter verilog
Verilog 编写的 计数器
- 用 verilog 编写的updown counter
counterfour
- verilog code for counter four
counter
- 关于FPGA实现的几种计数器的verilog源程序-FPGA implementation of several counter verilog source code
counter
- 用Verilog HDL语言实现FPGA的频率等精度测量。（已经过验证）-Using Verilog HDL language, such as FPGA frequency measurement accuracy. (Has already been verified)
counter
- verilog写的频率计程序的计数模块,-Verilog written procedures for counting frequency meter module,
Verilog--shiyanbaogao
- 有实验结果,用MOSIN6编写的,是Verilog HDL语言实现的. 练习三 利用条件语句实现计数分频时序电路 实验目的： 1. 掌握条件语句在简单时序模块设计中的使用； 2. 学习在Verilog模块中应用计数器； 3. 学习测试模块的编写、综合和不同层次的仿真。 练习四 阻塞赋值与非阻塞赋值的区别 实验目的： 1． 通过实验，掌握阻塞赋值与非阻塞赋值的概念和区别； 2． 了解阻塞赋值与非阻塞赋值的不同使用场合； 3． 学习测试模块的编写、综合和不同层
UpDownCounter
- 8-Bit Up Down Counter Verilog Code
sel_key
- verilog写的自动识别的加减计数器，挺好的，也算有自适应能力-Automatic Identification verilog written addition and subtraction counter, very good, and it has adaptive ability to count
verilog-counter
- 利用Verilog实现的数字钟和汽车尾灯，有闹钟，报时，置数等多种功能-Verilog
syncount
- synchronous counter in verilog
counter
- 用verilog写的计数器，可用于分频等多种功能。已经调试成功很好用-Written with verilog counter, can be used for frequency and other functions. Has been very good success with debugging
a_bcd_counter_using_verilog
- 3 bits bcd counter using verilog
verilog
- 包含了许多verilog编程的实用例子，且有运行之后的V文件，很完整-verilog
Counter_Design_Block
- Here is a code for a simple counter based on verilog
ds1621_latest.tar
- DS1621 verilog model with testing tasks. Testing elements assume the existence of the low level write/read (need to be written by the user) and include the macro tasks based on that write/read tasks. A test with macros is included. Only the Slope and
mod10asynchro
- this is a verilog code for asynchronous mod-10 counter.its also called a decade counter.
verilog
- 文件包含了寄存器，移位寄存器，可能计数器，计数器等用VHDL实现的功能模块。-File contains the register, shift register, may counter, counter, implemented with the VHDL modules.
time-counter
- 基于verilog的计时器源代码，可以通过编译-Verilog source code based on the timer, you can compile
VERILOG-COUNTER
- COUNTER DESIGN IN VERILOG