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树式除法型开方器VERILOG实现
- 树式除法型开方器VERILOG实现,用于任意长度的无符号数的开方运算,Square root of the tree-type divider-type device to achieve VERILOG
32bit.zip
- multiplier and divider verilog codes,multiplier and divider verilog codes
div.rar
- 除法器实验 verilog CPLD EPM1270 源代码,Experimental divider verilog CPLDEPM1270 source code
verilog-divider-code
- Verilog编写的分频器程序，包括偶数分频和奇数分频，作为参考。-verilog divider code
32_16div
- 这是一个简单的除法器（32bit/16bit),采用移位相减法-This is a simple divider (32bit/16bit), using phase shift subtraction
divider
- verilog HDL编写的浮点除法器，编译通过，可综合。压缩包包含三个文件。-verilog HDL write floating-point divider, compile, can be integrated. Archive contains three files.
div16
- 十六位的除法器，采用verilog hdl-16 of the divider using verilog hdl
divider
- 基于Verilog的除法器设计，可以直接在Q2里面运行哦~-Verilog-based design of the divider, which can be run directly in Q2 Oh ~
devider
- a divider design based on verilog language
divide
- It is n-bit sequential divider in verilog language
divider
- verilog divider hardware
div_n
- verilog占空比50奇偶任意 奇偶任意分频器！包括测试代码-verilog random duty cycle of 50 odd parity arbitrary divider! Including test code
Verilog
- 一些关于Verilog分频器设计.doc-Verilog divider design. Doc
verilog--divide-programs
- verilog任意分频程序，包括奇数倍分频和偶数倍分频，占空比为50 ，QuartusII上验证程序有效-verilog every divide programs, including an odd multiple divider and even multiple frequency, duty cycle 50 , the QuartusII on the verification process
divider
- verilog的除法器 有多重方法 很适合初级者阅读-verilog divider multiple method is very suitable for beginners to read
div1_feng
- 用verilog实现除法的功能，其中可以实现整数的除法，并有小数的表示。(verilog divider function ise fpga frequency)
verilog四则运算器
- verilog四则运算，包括加法器、乘法器、除法器，不过都是拾人牙慧，整理一下，供新手参考。(Verilog four operations, including the adder, multiplier and divider, but are written, tidy, for novice reference.)
Divider
- 用Verilog HDL语言实现分频器，初学，简单(The realization of frequency divider in Verilog HDL, Elementary learning is simple)
frequency divider and testbench
- a frequency divider and test bench with simulation results
VERILOG
- 基础的几个verilog代码实现，讲到case和task的使用。(basic verilog,use case and task ,very usual, i want some help to achieve the design of delta and sigma fractional_n divider.)