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verilog_example
- 九个verilog源码例子,包括寄存器,状态机等,含testbench-9 verilog source code examples, including registers, state machines, with testbench
Fsm
- 基于verilog的FSM设计,设计“101001”的序列检测器;包括testbench文件-The FSM based verilog design, design " 101001" sequence detector including testbench files