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Timer 8254 Verilog source code
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淺顯易懂的學習verilog程式基礎範例以時鐘為示範-Learn easy to understand the basic Verilog code for an example of a clock model
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Watchdog timer verilog RTL code
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Timer verilog RTL code
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verilog code for a microwave controller with clock output, clock time setting input, power control input+output, cooking timer setup, door open light, cooking complete buzzer output.
Four push buttons provide following active low input signal
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System watchdog verilog code
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基于verilog的计时器源代码，可以通过编译-Verilog source code based on the timer, you can compile
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本代码采用verilog HDL语言编写。实现的是数字跑表计时功能-The code using verilog HDL language. Implementation is a digital stopwatch timer functions
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篮球24s定时器的verilog代码，内涵代码以及程序逻辑说明-basketball 24s timer code of verilog
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this is a code of 8253 programme interval timer in verilog
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基于EDA软件平台上，用硬件描述语言verilog设计完成分频器、计数器、串行移位输出器、伪码发生器、QPSK I/Q调制器、QPSK I/Q解调器，基于选项法中频调制器，再将各个模块综合起来组成一个完整系统；并用quartusII软件对其进行仿真验证。-EDA software platform based on the hardware descr iption language verilog design complete shift of the frequency divider,
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数字时钟的verilog代码，以仿真编译通过，可直接用-Digital clock verilog code which is compiled and simulated and can be directly used
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本代码用verilog语言描述，在nios上操作，实现了定时器的设置和中断操作，并结合timestamp读取程序运行的时间。-The code to use verilog language to describe, in nios on operation, to achieve the timer settings and interrupt operation, combined with the timestamp reads the program run.
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Reaction Timer verilog code, can be downloaded on texas NEXYS2 or NEXYS3 board to test the reaction time by pressing the buttons.
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基于6M晶振FPGA的篮球24秒计时器verilog HDL代码，附testbench-Verilog HDL code for FPGA-based 6M crystal basketball 24 seconds timer, with testbench
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verilog source code of programable timer
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交通灯分为X组和Y组，每组包括了2位倒计时数码管和红黄绿三色LED信号灯（每组包括﹢、-两小组，显示内容一样），考虑到应用需求，要求芯片可通过I2C接口连接到上位机，以调节内部控制寄存器,此为Verilog代码，包含led、seg、timer等模块。-Traffic lights are divided into groups X and Y groups, each including two digital countdown yellow-green and red LED lights
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Verilog code of timer for APB
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是基于apb总线下的timer外设的rtl代码，主要包括apb_timer的master逻辑verilog，以及相应的开发文档，包括寄存器的描述，功能特性等。(RTL code is based on timer peripheral under APB bus, which mainly includes master logic Verilog of apb_timer and corresponding development documents, including the descr
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