搜索资源列表
VGAipcore
- vga ip core nios sopc
opb_vga.EDK下的用户IP核
- 一个EDK下的用户IP核，进行OPB总线到VGA的转换,EDK under a user IP core, the OPB bus to VGA conversion
SOPCVGAIP3090114
- 基于 SOPC 的 VGA IP 核设计-Based on SOPC the VGA IP core design
SOPCVGAIP
- 基于sopc的vga ip核设计参考文档-Based on SOPC vga ip-core design of the reference documentation
sopcip
- SOPC的IP核使用方法，介绍了好几种IP核的使用，供参考使用-SOPC to use the IP core, introduced several of the use of IP core for use and reference
vga_geometry_xps92i_s3_v01_00_03
- Here an embedded System-on-Chip is build, in an Xilinx Spartan-3 FPGA with Microblaze as the processor.A PLB core System is made with the VGA IP core attached to it. The software written for the MicroBlaze processor specifies the object, the color an
user_logic_VGA_Controller
- freeDev数字应用开发板中的VGA控制器的IP核的verilog实现-freeDev digital application development board of the VGA controller IP core implementation of the verilog
TERASIC_Binary_VGA_Controller
- 友晶公司提供的VGA Controller的IP核设计。针对的是DE2_70开发板。-Friends of the crystal provides the VGA Controller of the IP core design. Development board for the DE2_70.
vga_ip_v1_00_a
- This simple VGA ip core sample. This was implemented in Spartan3A-1800 Kit.-This is simple VGA ip core sample. This was implemented in Spartan3A-1800 Kit.
vga-ip-core
- vga ip core 资料 说明如定制一个ip核-vga ip core information such as a custom ip core
vga_display2
- VGA xian shi ip core ,qing cankao,duoxie-VGA xian shi ip core, qing cankao, duoxie
vgalcd
- vga ip核说明,包含寄存器手册及设计结构等-vga ip core
vga_gui
- VGA 的 ip core 编写程序时需要逐点编写-VGA-ip core programming point by point to write
vga_lcd
- VGA/LCD控制 ip核，支持 CRT LCD,支持多种色彩方案。-VGA/LCD control ip core, support CRT LCD, supports a variety of color schemes.
VGA_SW_Verilog
- VGA IP硬核设计，通过开关简单控制输出图像，在ISE14.6验证通过。-VGA IP hard-core design, the output image by a simple control switch, ISE14.6 validation.
FPGA IP cores
- FPGA IP cores on verilog for USB CY7C68013, VGA, Ethernet DM9000A, Sound WM8731.
colorbar
- VGA在800*600分辨率屏上显示竖型彩条10份，扫描时钟是通过例化IP核PLL_CLK进行分频得到40MHz-VGA color display type vertical strip 10 parts, scan clock by instantiating the IP core PLL_CLK performed on 800* 600 resolution screen frequency to be 40MHz