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Shifters_vhdl
- -- Title : Barrel Shifter (Pure combinational) -- This VHDL design file is an open design you can redistribute it and/or -- modify it and/or implement it after contacting the author -- You can check the draft license at --- Title : Barrel Shift
bioviewer-0.0.21
- A C++/SDL/OpenGL player for the Biovision .bvh file format, which stores hierarchical motion data commonly originating from motion capture hardware. Support for the Kaydara .fbx format (a general 3D interchange format) is planned.-A C / SDL / OpenGL
RAM_VHDL_34
- RAM之VHDL描述 RAM之VHDL描述-RAM's VHDL descr iption RAM's VHDL descr iption RAM's VH DL described in VHDL's RAM
sdgshjd
- 数字系统设计这是有关的相关源代码，有简易CPU 除法器、计数器等 ...[fpdiv_vhdl.rar] - 四位除法器的vhdl源程序 [vhdl范例.rar] - 最高优先级编码器8位相等比较器 三人表决器（三种不同的描述方式） 加法器描述 8位总线收发器：74245 （注2） 地址译码（for m68008） 多路选择器（使 BR> ... -Digital System Design This is the underlying source code, a simple C
vh
- 有用的VHDL源代码-useful VHDL source code
tlc549.数字电压表的VHDL语言实现
- 数字电压表的实现，VHDL语言实现，AD采用TLC549，通过学习，了解AD采集过程,The realization of digital voltage meter, VHDL language, AD using TLC549, by learning to understand the acquisition process AD
sha-1.rar
- 本算法基于leon2协处理器接口标准，内含testbench，在modelsim中仿真通过，在ise9.2中综合及后仿真通过。,The algorithm is based on the leon2 co-processor interface standard, including testbench, ModelSim simulation in the adoption, in ise9.2 integrated and adopted after the simulation.
DPLL(VHDL).rar
- 使用VHDL语言进行的数字锁相环的设计，里面有相关的文件，可以使用MUX+PLUS打开,The use of VHDL language of digital phase-locked loop design, there are relevant documents, you can use MUX+ PLUS Open
LPT.rar
- 实现开漏输出的并口，支持3.3V或5V，支持FPGA 的PS 配置功能。8位配置数据 自动移位输出，输入时钟24MHz，产生1MHz配置时钟。8位CPU数据总线接口， 11位地址总线。支持IO 的置位清除功能。,The realization of open-drain output of the parallel port, support 3.3V or 5V, support for FPGA configuration of the PS function. 8-bit config
ISA.rar
- pc104代码，这是本人调通过的。标准ISA通信接口，用VHDL编写,pc104 code, This is my tune adopted. ISA standard communication interface, using VHDL prepared
bcd.rar
- vhdl编写的将二进制转BCD码的程序.直接源代码，适合新手编程，语法学习,BCD
lcd_controler.rar
- 用FPGA设计12832中文液晶控制器,采用状态机的方式，提高稳定性！,FPGA cyclone control 12832LCD
LCD.rar
- 有限状态机的设计——LCD显示控制实验，用VHDL编写程序，整片报告,Finite state machine design- LCD display control experiments, using VHDL programming, the whole report
sinc3filter.rar
- 实现sinc3 FILTER的VHDL源码，还有实现SPI通讯的。,Sinc3 FILTER to achieve the VHDL source code, as well as the realization of SPI communication.
74LS160.rar
- 一个很实用的74系列的VHDL源码实例，可以很容易的学会VHDL语言,A series of 74 practical examples of VHDL source code, you can easily learn to VHDL language
SW_CODEC.rar
- SpaceWire Codec 程序,本软件只是和大家交流学习。仅供学习研究，严禁商用,SpaceWire Codec Source Vhdl
FPGA_PWM_VHDL.rar
- FPGA_EP2C5T144C8电机控制PWM、QUARTUS II 工程文件，非文本文件！可以直接使用！,FPGA_EP2C5T144C8 motor control PWM, QUARTUS II project file, non-text files! Direct access to!
fpga_drive_ad7892.rar
- 利用FPGA驱动12位的AD7892进行模数变换，并将数据存储到SRAM中。FPGA型号为EP1C3-144。并通过LED将12位AD值显示出来。,The use of FPGA-driven 12-bit AD7892 analog to digital conversion, and data is stored in the SRAM. FPGA model EP1C3-144. Through the LED will be 12-bit AD value is displayed.
CIC.rar
- cpld/fpga积分梳状滤波器(CIC)设计,cpld/fpga Integral comb filter (CIC) design