VHDL编写的七人表决器，有做课程设计的有福了-Written in VHDL seven voting machine, there are so blessed Oh curriculum design

用vhdl,设计的一个七人表决器，当赞成人数大于等于四时显示表决通过，同时分别将投票中赞成的人数和反对的人数在数码管上显示出来-VHDL design of a seven-vote in favor of the number of greater than or equal to four o' clock, the vote at the same time, respectively, displayed the number of people vote in favor of

EDA小程序，用VHDL语言设计七人表决器，四位加法器。-EDA small program design using VHDL seven people voting, four adder.

FPGA开发实例 之 用VHDL设计七人表决器-The FPGA development instance of the design with VHDL voter of seven people