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vhdl.rar
- 一个很好用的串口的VHDL实现。。quartus2编译通过,Serial port with a very good realization of VHDL. . quartus2 compiled through
par_serial-and-serial_par-VHDL
- 并入串出移位寄存器和8路并行输出串行移位寄存器的VHDL代码，经Quartus II 5.1验证可用,String into a shift register and 8-way parallel output serial shift register of the VHDL code, the Quartus II 5.1 can be used to verify
标准的串口通讯设计VHDL
- 标准的异步串口通讯设计程序——基于VHDL编程-communication design programme of standard asynchronous serial port base on VHDL programme
VHDL-SPI-Module.doc
- 本spi参数化通讯模块是一个支持SPI串行通信协议从协议的SPI从接口。可通过改变参数设置传输的位数，由外部控制器给定脉冲控制传输。-The parameters of spi communication module is a support SPI serial communication protocol from the agreement from the SPI interface. By changing the parameter settings can be transmit
serial
- -- 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在 --PC机上安装一个串口调试工具来验证程序的功能。 -- 程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控 --制器，10个bit是1位起始位，8个数据位，1个结束 --位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实 --现相应的波特率。程序当前设定的div_par 的值是0x104，对应的波特率是 --9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时
serial
- 基于VHDL的串口通信 基于VHDL的串口通信-VHDL-based serial communication based on VHDL Serial Communication
SIPO
- Filo Serial-Input to Paralle-output
serial
- 利用VHDL语言编写的串口程序，可以在Quartus2环境下编译下载-Use the serial language VHDL program can be compiled in an environment Quartus2 Download
mux_reg
- VHDL code for a multiplexer and a parallel/serial in parallel/serial out shift register
quartus
- des algorithm send rx from serial port
serial
- 串口程序，具有起始位，数据位，停止位（无奇偶校验位）-serial program
vhdl
- vhdl代码串口的实现,每个部分的代码别写好了，元件例化一下即可用，-my english is poor ,i hope this make you understand and help you this is Serial implementation vhdl Categories:hardware
vhdl
- VHDL语言的UART串行接口芯片设计程序清单 附录1 数据接收据器的VHDL语言描述清单-vhdl serial
serial
- 串行转并行的VHDL源代码，结构化编程，学习模块化编程和实用性都很大。-Serial transfer parallel VHDL source code, structured programming, modular programming and practical learning are great.
ade
- 用VERILOG HDL 语言实现一个8位串行乘法器-VERILOG HDL language with an 8-bit serial multiplier
UART
- VHDL语言写的串口发送、接收程序，根据晶振和相应的波特率修改分频器就可以实现！-Written in VHDL serial send, receive, process, according to crystal and the corresponding baud rate divider changes can be achieved!
VHDL
- 序列检测器设计VHDL源程序 任意输入串行数据串-VHDL source code sequence detector design arbitrary string of serial data input
serial-adder
- VHDL code for adding two hard-coded 8-bit binary numbers
vhdl-serial
- VHDL串口通信,实现数据的发送与接收，适合FPGA和CPLD芯片的开发-VHDL serial communication
VHDL-serial-communication-program
- VHDL串口通信程序设计 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。-VHDL serial communication program design Function of this module is to verify the implementation and the basic functions of a PC serial communications. We need to install a seria