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viterbi
- (2,1,9)卷积编解码器，译码部分采用Vitebi译码算法，设计使用Verilog HDL语言，在Modelsim平台下仿真通过
viterbigen
- viterbi verilog 代码生成程序，产生多项式可自由指定
viterbi.v
- viterbi的verilog文件，很实用的。
(2,1,3)卷积码编解码
- (2,1,3)卷积码编解码，viterbi译码
viterbi译码
- verilog源代码
viterbi.rar
- 这是一个用VERILOG HDL语言编写的viterbi译码程序,This is a language VERILOG HDL by the viterbi decoding process
viter2
- verilog实现卷积码的译码，viterbi算法-verilog to achieve the decoding convolutional codes, viterbi algorithm
viterbi
- verilog程序，实现了（2，1，4）卷积码编码，和基于回溯算法的维特比译码器-verilog program to achieve the (2,1,4) convolutional code encoding, and algorithm based on the back of the Viterbi decoder
viterbi
- 一个vitrtbi算法的参考实现,verilog的-A reference implementation vitrtbi algorithm, verilog of
viterbi
- viterbi encoder and decoder modeling verilog
viterbi
- Viterbi verilog generator
Viterbi_decoder
- Viterbi译码器的编解码器的设计 用Verilog实现-Viterbi decoder。Verilog
viterbidecoder
- viterbi译码器的Verilog实现,(3,1,7)零尾卷积码-viterbi decoder implementation by verilog HDL （3，1，7）zero tail conventional code
viterbi
- verilog code for viterbi encoder and decoder
viterbi
- This a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is w
viterbi
- 硬判决viterbi译码的硬件实现，通过verilog语言。采用回溯的方法。回溯深度为16.-Hard decision viterbi decoding in hardware, through the verilog language. A retrospective approach. Back depth is 16.
Viterbi_check
- It is a verilog code for viterbi decoding with trellis diagram
Viterbi-verilog-codes
- viterbi的无线局域网802.11协议接收端重要的一步。该资料为viterbi的verilog代码，它占用的资源相对比较低，而性能又高。-the viterbi wireless LAN 802.11 receiving end the important step. The viterbi verilog code, it takes up resources is relatively low, and high performance.
viterbi-decoder-verilog
- viterbi verilog implemetation based matlab-viterbi verilog implemetation based matlab