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  1. electric-8.08

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  2. The ElectricTM VLSI Design System is an open-source Electronic Design Automation (EDA) system that can handle many forms of circuit design, including: * Custom IC layout * Schematic Capture (digital and analog) * Textual Languages such a
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-06-08
    • 文件大小:14.67mb
    • 提供者:杨晓斐
  1. ENCODINGMETHOD

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  2. The sequence-pair was proposed to represent a rectangle packing and a placement, and is used to place modules automatically in VLSI layout design. Several decoding methods of sequence-pair were proposed. However, encoding methods are not foun
  3. 所属分类:Windows Develop

    • 发布日期:2017-04-25
    • 文件大小:98.89kb
    • 提供者:aditi2000
  1. gcl.src.tar

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  2. BOI version of Steiner tree construction, practical and popular for manhattan VLSI routing, generate a Steiner minimum tree for given set of terminals in a layout plane-BOI version of Steiner tree construction, practical and popular for manhattan VLS
  3. 所属分类:Post-TeleCom sofeware systems

    • 发布日期:2017-04-03
    • 文件大小:357.39kb
    • 提供者:Ernesto Liu
  1. buf_tree_pol.tar

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  2. Construct buffered routing tree for VLSI interconnects in a Manhanttan layout plane for a given set of terminals, guarantee polarity of the terminals agree with each other
  3. 所属分类:Post-TeleCom sofeware systems

    • 发布日期:2017-04-02
    • 文件大小:32.73kb
    • 提供者:Ernesto Liu
  1. FengShui.tar

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  2. FengShui: custom ASIC layout placement for gigascale VLSI circuits, for gate array, sea of gate and standard cell designs, scales well into million gate designs-FengShui: custom ASIC layout placement for gigascale VLSI circuits, for gate array, sea
  3. 所属分类:Post-TeleCom sofeware systems

    • 发布日期:2017-04-07
    • 文件大小:571.43kb
    • 提供者:Ernesto Liu
  1. 038736837X

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  2. Modern Circuit Placement: Best Practices and Results describes advanced techniques in VLSI circuit placement which is one of the most important steps of the VLSI physical design flow. Physical design addresses the back-end layout stage of the chip de
  3. 所属分类:SCM

    • 发布日期:2017-06-03
    • 文件大小:14.48mb
    • 提供者:朋友
  1. MNTH

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  2. 在管理科学、计算机科学、分子物理学、生物学、超大规模集成电路设计、代码设计、图像处理和电子工程等领域中,存在着大量的组合优化问题。例如,货郎担问题、最大截问题、0—1背包问题、图着色问题、设备布局问题以及布线问题等,这些问题至今仍未找到多项式时间算法。-In management science, computer science, molecular physics, biology, VLSI design, code design, image processing and electro
  3. 所属分类:Special Effects

    • 发布日期:2017-03-27
    • 文件大小:180.93kb
    • 提供者:张浩
  1. CMOS-TannerPL-Edit

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  2. 主要内容: • 版图设计概念; • CMOS VLSI制造工艺; • Tanner版图流程举例(反相器)。-Main content: • layout design concepts • CMOS VLSI manufacturing process • Tanner map of the process instance (inverter).
  3. 所属分类:software engineering

    • 发布日期:2017-04-06
    • 文件大小:565.74kb
    • 提供者:kro
  1. Oracle-cloud-computing-strategy.pdf

    1下载:
  2. Oracle 云计算战略 • 提供私有云和公有云两种解决方案供客户选择 • 提供全面、集成的 SaaS、PaaS 和 IaaS 产品 • 让客户根据业务需要采用云 最小面积的矩形。由于各种包装 是不可数无穷的,成功优化的关键问题 是有限的解空间的引进,其中包括一个 最佳解决方案。本文提出了这样一个解决方案空间 每个包装的代表由一对模块的名称序列, 被称为序列对。通过模拟搜索这个空间 退火,数百个模块已挤满有效地 证明
  3. 所属分类:File Formats

    • 发布日期:2017-03-29
    • 文件大小:676.45kb
    • 提供者:jame
  1. bantu-VLSI-ASIC

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  2. 版图设计技术,超大规模集成电路,ASIC集成电路等课程知识,涵盖版图设计过程、前期准备工作、常用编辑软件、CMOS IC等.-Layout techniques, VLSI, ASIC integrated circuits and other curriculum knowledge, covering the territory of the design process, the preparatory work, commonly used editing software, CMOS
  3. 所属分类:Project Design

    • 发布日期:2017-05-08
    • 文件大小:1.89mb
    • 提供者:yoyo
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