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pulse-VHDL
- 可控脉冲产生ＶＨＤＬ程序 开发软件ＩＳＥ，程序通过了器件后仿真并在芯片ＸＣ９５７２中实现了-controllable pulse generated VHDL ISE software development procedures, procedures adopted after the simulation devices and chips to achieve the XC9572
xc9572_1
- xilinx xc9572 cpld 实现的伺服电机控制器，电机控制输出，和增量编码器读取。-Xilinx xc9572 cpld achieve servo motor controller, motor control output, Incremental encoder and the reader.
XC9572shixianHDB3bianma
- 用XC9572实现HDB3编解码设计 用XC9572实现HDB3编解码设计-using XC9572 achieve HDB3 CODEC designed for XC9572 achieve HDB3 CODEC Design With XC9572 achieve HDB3 CODEC Design
xc9572c51
- 用XC9572来控制LCD12864的读\\写等时序,用89C52的总线方式来控制LCD
A01
- 利用XC9572-TQFP100(Xilinx CPLD)制作的多功能CPLD/FPGA的ISP下载线源代码及线路图。可用来烧录Xilinx,Lattice,Altera等厂家的CPLD/FPGA.-Using XC9572-TQFP100 (Xilinx CPLD) produced by multi-CPLD/FPGA download cable ISP in the source code and circuit diagram. Burning can be used to Xilin
guard_against_theft
- 利用XC9572－PQ44（Xilinx CPLD）制作的一款家用防盗报警器的Verilog源代码及原理图，当房门打开后，15秒内若没有按下Key1,则会自动拨打设定手机号（当然，要另连接一台手机）-Using XC9572-PQ44 (Xilinx CPLD) produced by a home burglar alarm of the Verilog source code and the schematic diagram, when the door opened, within 15
CPLD-XC9572-PIN-ASSIGNMENTS
- ITS and simple low power program
xc9572
- Project frequency inverter for induction motors
disp_mux1
- CPLD XC9572 BCD Calculater
MGR2
- 窄脉冲发生器-51单片机源程序，该方案是用一片AT89S52与XILINX公司XC9572组成电路，能产生1~1000微妙脉冲宽度，频率100赫兹到99KHz的可调脉宽和频率的脉冲波--51 Single-chip narrow-pulse generator source, the program is an integral AT89S52 with XILINX' s XC9572 circuit, to produce a 1000 subtle pulse width, freq
xc9572_IO
- xc9572应用扩展8051等的地址线，以及扩展更多的IO口用-xc9572 application extension 8051 address lines, and extended more IO port
9536
- Xilinx user constraints file for the cpld xc9536 or xc9536xl or xc9572 or xc9572xl
oscilloscope.ZIP
- Oscilloscop project on PIC18F4550 and XC9572. LCD 320x240 on SED1335 driver
PWM
- pwm PWM.ise Implementation State: Module Name: PWM Target Device: xc9572-10PC84