搜索资源列表
PCIE_DMA_DDR3_verilog_design
- 基于xilinx fpga的pci-e到dma再到ddr3的数据传输完整设计-PCIE_DMA_DDR3 verilog reference design
11_ddr3_test
- spartan6 ddr3 test with FPGA communicate
XILINX_DDR3_IP核使用教程
- 详细介绍了Xilinx DDR3 IP核的使用方法和注意事项(The usage and attention of Xilinx DDR3 IP core are introduced in detai)
DDR3_A4
- xilinx FPGA A7 驱动DDR3的DEMO例程(DEMO routines driven by Xilinx FPGA A7 for DDR3)
test_ddr3
- 基于XILINX K7系列FPGA实现5120*5120分辨率20帧的DDR3读写,发送到海思3559,HDMI显示。(Based on Xilinx K7 series FPGA to achieve 5120*5120 resolution of 20 frames of DDR3 read and write, sent to the Hays 3559,HDMI display.)