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finalcoursework
- 用VHDL代码写的模拟微处理器核程序,有计算模块和register file 等模块,并包含测试程序,调试程序 ACTIVE HDL-Simulation with the VHDL code is written in the microprocessor core procedures, such as computing modules, and register file module, and includes test program, the debugger ACTIVE HDL