查看会员资料
用 户 名:康***
发送消息- Email:用户隐藏
- Icq/MSN:
- 电话号码:
- Homepage:
- 会员简介:
最新会员发布资源
DesignCompilerPPT
- 用design compiler对verilog hdl的程序进行逻辑综合最后生成门级网表即用门生成的电路图。-Verilog hdl with design compiler of the logic synthesis procedure generates the final gate-level netlist that is generated with the door circuit.