查看会员资料
用 户 名:胡***
发送消息- Email:用户隐藏
- Icq/MSN:
- 电话号码:
- Homepage:
- 会员简介:
最新会员发布资源
remove_dc_input_tieoffs
- Design Compile综合RTL时,工具默认将tie 0的port优化掉,运用此脚本,可以将tie 0的port保持住。-When do synthesis, Design Compiler will optimize the tie 0 ports as default. This tool/scr ipt can keep the tie 0 ports in the output netlist.