文件名称:1-D-DWT_verilog-code
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Image compression is one of the prominent topics in image processing that plays a very important role in
reducing image size for real-time transmission and storage. Many of the standards recommend the use of DWT
for image compression. The computational complexity of DWT imposes a major challenge for the real-time use
of DWT-based image compression algorithms. In this paper, we propose a modified lifting scheme for
computing the approximation and detailed coefficients of DWT. The modified equations use, right shift
operators and 6-bit multipliers. The hierarchy levels in computation are reduced to one thereby minimizing the
delay and increasing throughput. The design implemented on Virtex-5 FPGA operates at 180 MHz and
consumes less than 1W of power. The design occupies less than 1 of the LUT resources on FPGA. The
architecture developed is suitable for real-time image processing on FPGA platform.
-Image compression is one of the prominent topics in image processing that plays a very important role in
reducing image size for real-time transmission and storage. Many of the standards recommend the use of DWT
for image compression. The computational complexity of DWT imposes a major challenge for the real-time use
of DWT-based image compression algorithms. In this paper, we propose a modified lifting scheme for
computing the approximation and detailed coefficients of DWT. The modified equations use, right shift
operators and 6-bit multipliers. The hierarchy levels in computation are reduced to one thereby minimizing the
delay and increasing throughput. The design implemented on Virtex-5 FPGA operates at 180 MHz and
consumes less than 1W of power. The design occupies less than 1 of the LUT resources on FPGA. The
architecture developed is suitable for real-time image processing on FPGA platform.
reducing image size for real-time transmission and storage. Many of the standards recommend the use of DWT
for image compression. The computational complexity of DWT imposes a major challenge for the real-time use
of DWT-based image compression algorithms. In this paper, we propose a modified lifting scheme for
computing the approximation and detailed coefficients of DWT. The modified equations use, right shift
operators and 6-bit multipliers. The hierarchy levels in computation are reduced to one thereby minimizing the
delay and increasing throughput. The design implemented on Virtex-5 FPGA operates at 180 MHz and
consumes less than 1W of power. The design occupies less than 1 of the LUT resources on FPGA. The
architecture developed is suitable for real-time image processing on FPGA platform.
-Image compression is one of the prominent topics in image processing that plays a very important role in
reducing image size for real-time transmission and storage. Many of the standards recommend the use of DWT
for image compression. The computational complexity of DWT imposes a major challenge for the real-time use
of DWT-based image compression algorithms. In this paper, we propose a modified lifting scheme for
computing the approximation and detailed coefficients of DWT. The modified equations use, right shift
operators and 6-bit multipliers. The hierarchy levels in computation are reduced to one thereby minimizing the
delay and increasing throughput. The design implemented on Virtex-5 FPGA operates at 180 MHz and
consumes less than 1W of power. The design occupies less than 1 of the LUT resources on FPGA. The
architecture developed is suitable for real-time image processing on FPGA platform.
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下载文件列表
DWT的Verilog code/2Ddwt_ALL/01.raw
DWT的Verilog code/2Ddwt_ALL/02.raw
DWT的Verilog code/2Ddwt_ALL/02.raw.bak
DWT的Verilog code/2Ddwt_ALL/2D_F97_B.raw
DWT的Verilog code/2Ddwt_ALL/BABOO64.raw
DWT的Verilog code/2Ddwt_ALL/Debug/Psnr.exe
DWT的Verilog code/2Ddwt_ALL/Debug/Psnr.ilk
DWT的Verilog code/2Ddwt_ALL/Debug/Psnr.obj
DWT的Verilog code/2Ddwt_ALL/Debug/Psnr.pch
DWT的Verilog code/2Ddwt_ALL/Debug/Psnr.pdb
DWT的Verilog code/2Ddwt_ALL/Debug/save_FPGAtoPC.exe
DWT的Verilog code/2Ddwt_ALL/Debug/save_FPGAtoPC.ilk
DWT的Verilog code/2Ddwt_ALL/Debug/save_FPGAtoPC.obj
DWT的Verilog code/2Ddwt_ALL/Debug/save_FPGAtoPC.pch
DWT的Verilog code/2Ddwt_ALL/Debug/save_FPGAtoPC.pdb
DWT的Verilog code/2Ddwt_ALL/Debug/SendPctoFPGA.exe
DWT的Verilog code/2Ddwt_ALL/Debug/SendPctoFPGA.ilk
DWT的Verilog code/2Ddwt_ALL/Debug/SendPctoFPGA.obj
DWT的Verilog code/2Ddwt_ALL/Debug/SendPctoFPGA.pch
DWT的Verilog code/2Ddwt_ALL/Debug/SendPctoFPGA.pdb
DWT的Verilog code/2Ddwt_ALL/Debug/vc60.idb
DWT的Verilog code/2Ddwt_ALL/Debug/vc60.pdb
DWT的Verilog code/2Ddwt_ALL/EARTH128.raw
DWT的Verilog code/2Ddwt_ALL/EARTH128.raw.bak
DWT的Verilog code/2Ddwt_ALL/Kent_End.raw.bak
DWT的Verilog code/2Ddwt_ALL/LENA128.raw
DWT的Verilog code/2Ddwt_ALL/LENA64(no).raw
DWT的Verilog code/2Ddwt_ALL/LENA64(no).raw.bak
DWT的Verilog code/2Ddwt_ALL/LENA64.raw
DWT的Verilog code/2Ddwt_ALL/LENA64.raw.bak
DWT的Verilog code/2Ddwt_ALL/Psnr.cpp
DWT的Verilog code/2Ddwt_ALL/Psnr.dsp
DWT的Verilog code/2Ddwt_ALL/Psnr.dsw
DWT的Verilog code/2Ddwt_ALL/Psnr.ncb
DWT的Verilog code/2Ddwt_ALL/Psnr.opt
DWT的Verilog code/2Ddwt_ALL/Psnr.plg
DWT的Verilog code/2Ddwt_ALL/RAW/2D1L/2D_F1L_Col.raw
DWT的Verilog code/2Ddwt_ALL/RAW/2D1L/2D_F1L_Row.raw
DWT的Verilog code/2Ddwt_ALL/RAW/2D1L/2D_I1L_ReSource.raw
DWT的Verilog code/2Ddwt_ALL/RAW/2D1L_ReSource.raw
DWT的Verilog code/2Ddwt_ALL/RAW/2D2L/2D_F2L_Col.raw
DWT的Verilog code/2Ddwt_ALL/RAW/2D2L/2D_F2L_Row.raw
DWT的Verilog code/2Ddwt_ALL/RAW/2D2L/2D_F2L_Row_to_Resource.raw
DWT的Verilog code/2Ddwt_ALL/RAW/2D2L/2D_FI2L_ReSource.raw
DWT的Verilog code/2Ddwt_ALL/save_FPGAtoPC.cpp
DWT的Verilog code/2Ddwt_ALL/save_FPGAtoPC.dsp
DWT的Verilog code/2Ddwt_ALL/save_FPGAtoPC.opt
DWT的Verilog code/2Ddwt_ALL/save_FPGAtoPC.plg
DWT的Verilog code/2Ddwt_ALL/SendPctoFPGA.cpp
DWT的Verilog code/2Ddwt_ALL/SendPctoFPGA.dsp
DWT的Verilog code/2Ddwt_ALL/SendPctoFPGA.opt
DWT的Verilog code/2Ddwt_ALL/SendPctoFPGA.plg
DWT的Verilog code/2Ddwt_ALL/text_02.raw
DWT的Verilog code/2Ddwt_ALL/text_02.raw.bak
DWT的Verilog code/2Ddwt_ALL/RAW/2D1L
DWT的Verilog code/2Ddwt_ALL/RAW/2D2L
DWT的Verilog code/2Ddwt_ALL/Debug
DWT的Verilog code/2Ddwt_ALL/RAW
DWT的Verilog code/2Ddwt_ALL
DWT的Verilog code
DWT的Verilog code/2Ddwt_ALL/02.raw
DWT的Verilog code/2Ddwt_ALL/02.raw.bak
DWT的Verilog code/2Ddwt_ALL/2D_F97_B.raw
DWT的Verilog code/2Ddwt_ALL/BABOO64.raw
DWT的Verilog code/2Ddwt_ALL/Debug/Psnr.exe
DWT的Verilog code/2Ddwt_ALL/Debug/Psnr.ilk
DWT的Verilog code/2Ddwt_ALL/Debug/Psnr.obj
DWT的Verilog code/2Ddwt_ALL/Debug/Psnr.pch
DWT的Verilog code/2Ddwt_ALL/Debug/Psnr.pdb
DWT的Verilog code/2Ddwt_ALL/Debug/save_FPGAtoPC.exe
DWT的Verilog code/2Ddwt_ALL/Debug/save_FPGAtoPC.ilk
DWT的Verilog code/2Ddwt_ALL/Debug/save_FPGAtoPC.obj
DWT的Verilog code/2Ddwt_ALL/Debug/save_FPGAtoPC.pch
DWT的Verilog code/2Ddwt_ALL/Debug/save_FPGAtoPC.pdb
DWT的Verilog code/2Ddwt_ALL/Debug/SendPctoFPGA.exe
DWT的Verilog code/2Ddwt_ALL/Debug/SendPctoFPGA.ilk
DWT的Verilog code/2Ddwt_ALL/Debug/SendPctoFPGA.obj
DWT的Verilog code/2Ddwt_ALL/Debug/SendPctoFPGA.pch
DWT的Verilog code/2Ddwt_ALL/Debug/SendPctoFPGA.pdb
DWT的Verilog code/2Ddwt_ALL/Debug/vc60.idb
DWT的Verilog code/2Ddwt_ALL/Debug/vc60.pdb
DWT的Verilog code/2Ddwt_ALL/EARTH128.raw
DWT的Verilog code/2Ddwt_ALL/EARTH128.raw.bak
DWT的Verilog code/2Ddwt_ALL/Kent_End.raw.bak
DWT的Verilog code/2Ddwt_ALL/LENA128.raw
DWT的Verilog code/2Ddwt_ALL/LENA64(no).raw
DWT的Verilog code/2Ddwt_ALL/LENA64(no).raw.bak
DWT的Verilog code/2Ddwt_ALL/LENA64.raw
DWT的Verilog code/2Ddwt_ALL/LENA64.raw.bak
DWT的Verilog code/2Ddwt_ALL/Psnr.cpp
DWT的Verilog code/2Ddwt_ALL/Psnr.dsp
DWT的Verilog code/2Ddwt_ALL/Psnr.dsw
DWT的Verilog code/2Ddwt_ALL/Psnr.ncb
DWT的Verilog code/2Ddwt_ALL/Psnr.opt
DWT的Verilog code/2Ddwt_ALL/Psnr.plg
DWT的Verilog code/2Ddwt_ALL/RAW/2D1L/2D_F1L_Col.raw
DWT的Verilog code/2Ddwt_ALL/RAW/2D1L/2D_F1L_Row.raw
DWT的Verilog code/2Ddwt_ALL/RAW/2D1L/2D_I1L_ReSource.raw
DWT的Verilog code/2Ddwt_ALL/RAW/2D1L_ReSource.raw
DWT的Verilog code/2Ddwt_ALL/RAW/2D2L/2D_F2L_Col.raw
DWT的Verilog code/2Ddwt_ALL/RAW/2D2L/2D_F2L_Row.raw
DWT的Verilog code/2Ddwt_ALL/RAW/2D2L/2D_F2L_Row_to_Resource.raw
DWT的Verilog code/2Ddwt_ALL/RAW/2D2L/2D_FI2L_ReSource.raw
DWT的Verilog code/2Ddwt_ALL/save_FPGAtoPC.cpp
DWT的Verilog code/2Ddwt_ALL/save_FPGAtoPC.dsp
DWT的Verilog code/2Ddwt_ALL/save_FPGAtoPC.opt
DWT的Verilog code/2Ddwt_ALL/save_FPGAtoPC.plg
DWT的Verilog code/2Ddwt_ALL/SendPctoFPGA.cpp
DWT的Verilog code/2Ddwt_ALL/SendPctoFPGA.dsp
DWT的Verilog code/2Ddwt_ALL/SendPctoFPGA.opt
DWT的Verilog code/2Ddwt_ALL/SendPctoFPGA.plg
DWT的Verilog code/2Ddwt_ALL/text_02.raw
DWT的Verilog code/2Ddwt_ALL/text_02.raw.bak
DWT的Verilog code/2Ddwt_ALL/RAW/2D1L
DWT的Verilog code/2Ddwt_ALL/RAW/2D2L
DWT的Verilog code/2Ddwt_ALL/Debug
DWT的Verilog code/2Ddwt_ALL/RAW
DWT的Verilog code/2Ddwt_ALL
DWT的Verilog code
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