资源列表
用Verilog描述路径延迟模块
- 用Verilog语言的specify语句编写实现路径延迟模块的程序(Write the program of implementing path delay module with the specify statement of Verilog language.)
VB_百叶窗式显示图片
- VB源代码,本代码演示百叶窗式显示背景图片(Shutter window display)
include1
- 一个农夫在河边带了一只狼、一只羊和一颗白菜，他需要把这三样东西用船带到河的对岸。然而，这艘船只能容下农夫本人和另外一样东西。如果农夫不在场的话，狼会吃掉羊，羊也会吃掉白菜。(A farmer took a wolf, a sheep and a cabbage on the riverside. He needed to take the three things to the opposite side of the river by boat. However, the boat can o
5480848
- QQ通讯协议1 1模块,很不错的易语言模块,易爱好者可以下载使用()
modbus4j-master
- modbus4j实现了Java与modbus协议的以下几种通讯方式: modbus TCP/IP通讯 modubs UDP/IP通讯 modbus RTU/IP通讯(modbus4j: modbus TCP/IP modubs UDP/IP modbus RTU/IP)
vecterditecteddelegation
- RGB_CMYK颜色值互换易语言源码,很不错的易语言源码,适合易语言爱好者学习,()
SVPWM_and_SPWM
- z源逆变器svpwm控制模块及其spwm控制模块(svpwm Control module and spwm control module of Z source inverter)
4位BCD计数器
- 用Verilog语言编程实现4位BCD计数器的功能(Write the programm with Verilog language to implement the function of 4 - bit BCD counter.)
04_led_test
- xilinx fpga verilog
免迭代cordic及误差分析
- 一种免迭代的cordic算法及误差分析,结果运行正确(an itration-free algorithm of cordic and error analysis)
systemc-2.1.v1
- systemc开发环境搭，从而可以通过systemc语言实现电路的设计以及仿真(Build the development environment for systemc so that the circuit design and simulation can be implemented using the systemc language.)
FileTool
- 用于解决VC6.0与Windows7不兼容问题，主要针对文件打开与加载导致VC崩溃的问题(Used to solve the problem of incompatibility between VC6.0 and Windows 7, mainly for the problem of file opening and loading causing VC to crash)