资源列表
shuzizhong
- 大学VHDL实验数字钟源码，有的专业数字电路实验设计也有要求做的。-University of VHDL experimental digital clock source, and some professional digital circuit design has also requested to do so.
seriall2parallel
- its code for converting serial to parallel processing data
gold
- 基于vhdl语言的15位gold序列的设计的开端一部分程序-Vhdl language based on sequences of the 15 gold as part of the beginning of the design process
park
- 这是一个关于Park变换的程序,希望对大家能有所帮助-This is about a Park transform procedures, we hope to help
jjj
- 库文件实现的单片机的转换 我也不是很清楚-it is a file sorry i do not konw what is is?
key
- 实现4*4 16小键盘的扫描，每按下一个按键，相应的lED灯亮一下-o shit
20120918-1653
- 上位机，一个简单的数据更改程序，用于参数设定等-Epistatic machine, a simple data change program, used for parameter setting, etc
RAM_VHDL
- 用VHDL描述了一个32KBit的独立的读写时钟、使能、地址的双口RAM，-VHDL descr iption of a 32KBit with independent read and write clock, enable, address the dual-port RAM,
fenping_VHDL
- 这是一个任意分频器 稍微改动里面的数据 就可以进行分频（VHDL编写）-This is a slightly altered any data inside divider can be divided by (VHDL written)
Freq
- 89C52单片机输出方波，可以用两个独立按键调整频率大小-89C52 microcontroller output square wave, you can use two separate buttons to adjust the frequency size
BTO
- 这是一个十六进制显示译码器，可在EDA板子上实现，希望对大家有帮助-This is a hexadecimal display decoder may be implemented on EDA board, we hope to help
practica1
- tester.vhd library IEEE use IEEE.STD_LOGIC_1164.all use IEEE.STD_LOGIC_ARITH.all use IEEE.STD_LOGIC_UNSIGNED.all LIBRARY lpm USE lpm.lpm_components.ALL entity practica1 is port ( RESET : in std_logic clk :