资源列表
COUNT_10
- VHDL源代码.设计一个带有异步清0功能的十进制计数器。计数器时钟clk上升沿有效，清零端为clrn,进位输出为co。 -VHDL source code. Asynchronous design with a 0-counter function of the metric system. Counter clock clk ascending effective end to reset clrn, rounding output co.
dsp
- DSP 典型浮点数处理的例子 供参考设计，有很大的借鉴哦
rom
- 基于vhdl的rom的描述,经过确定测试通过.
flash
- fpga的FLASH读写VERILOG代码。希望对大家有用-the verilog code of fpga read/write flash
evmdm6437_aic33_opencodec
- TMS320DM6437下的evmdm6437_aic33_opencodec！很有学习价值-evmdm6437_aic33_opencodec
txmit
- 异步串口发送模块，数据位8位，一位起始位一位结束位-Send asynchronous serial module, 8 data bits, one bit a the end of the start bit
main
- Simplest VHDL code, flashing LEDs, for spartan 3an7-Simplest VHDL code, flashing LEDs, for spartan 3an700
font
- font code for 12864 lcd
syn_fifo
- 同步FIFO的源代码（单时钟），使用SystemVerilog语言实现-Synchronous (single clock) FIFO，using SystemVerilog
74ls299
- VHDL code for IC 742-VHDL code for IC 74299
RAOM
- 此包为两个程序，一个为八三编码器，一个为RAM存储器，程序完全能运行-This package of two programs, one for 83 encoder, a RAM memory, the program is fully capable of running
traffic-lights
- 基于单片机的交通灯设计，可以做为学生的毕业设计参考，-Microcontroller-based design of traffic lights, you can refer to learning