资源列表
ClockOut
- 通过VERILOG编程，实现FPGA任意整数分频的源代码-through verilog programming, FPGA arbitrary integer frequency of the source code
kbd_routines
- 2x3 Keypad libraries for CCS PIC-C users
keyscan_test
- 针对机械式按键存在的抖动问题，用verilog HDL编写了一个采用防抖方案并对按键次数计数的模块，已经在ISE综合通过！-Keys exist for mechanical jitter, with verilog HDL prepared a program with anti-shake button and count the number of modules have been integrated by ISE!
sipo
- Serial In Parallel Out Shift Register in VHDL in Modelsim
traficlight
- avr单片机，通过数码管和led小灯实现交通灯，在15秒小灯变红（通过不同小灯亮表示），倒计时-avr microcontroller, digital control and led by a small lamp to achieve the traffic lights, small lights red in 15 seconds (indicated by different small lights), the countdown
LTC1407A
- LTC1407A仿真 可以模拟其全部功能 具有单端输入 时钟 串行输出-LTC1407A simulation can simulate all the functions in its single-ended input clock serial output
TAXI
- 基于VHDL的出租车计费器，通过VHDL语言来编程实现计费系统的四个功能块：分频模块，控制模块，计量模块和译码显示模块，最后使用MAX+PLUSII软件来对程序进行仿真，以模拟实现出租车的启动，停止以及等待等过程中的计时，计程和计费功能。-Taxi meter based on VHDL, VHDL language programming through the billing system of the four functional blocks: frequency module, co
PWM
- PWM输出,用PWM方式产生可控制点空比的方波。。可用来驱动步进电机等。-PWM OUT
rsa
- 经典的RSA加密以及解密，在VC环境或者dos环境均可运行。-Classical RSA encryption and decryption, the VC environment or dos environment can run.
steganography
- data hiding in audio signal, using matlab
decode
- 通信数据中FM0数据的解码接收，解码数据和输出同步时钟。Verilog HDL-FM0 decoding the received data in the communication data, the decoded data and outputs sync clock。Verilog HDL
chuankoushoufa
- zigbee串口收发实验的代码，让CC2530开发板的数据可以通过串口发送到电脑-ZigBee serial port to send and receive experiments code, so that the data CC2530 development board can send to the computer through the serial port