资源列表
Griphics2D
- 用路径算法实现了Graphics2D图形的编程-path algorithm using a graphical programming Graphics2D
chuanbing
- 自己编写的串并变换的fpga程序，使用verilog语言-I have written FPGA series and transform, the use of Verilog language
32ET_source
- 32时隙的VHDL源代码 在开发E1 2M线路的时候非常有用-32 slot of the VHDL source code in the development of E1 2M lines is very useful when
uart_receiver
- This UART Receiver interface C code Tested on Sparton 3 xilinx FPGA.-This is UART Receiver interface C code Tested on Sparton 3 xilinx FPGA.
mn
- 模拟串口8位数码管显示时钟程序 模拟串口8位数码管显示时钟程序-Serial 8-bit analog digital tube display clock program to simulate serial port 8-bit digital tube display clock program
key
- 4*4键盘扫描VHDL程序，程序中有产生键值，值得参考-heguo
35_bit_pack
- hiiiiiSystem will automatically delete the directory of debug and release, so please do not put files on these two directory
calibration
- CS5460校准程序，控制器为C8051F310，SPI通信协议，可以作为电表芯片示例-CS5460 calibration procedure, the controller for the C8051F310, SPI communication protocol, as the meter chip sample
ad
- DSP2407，AD转换程序。AD采样频率为12K，采样模式采用顺序采样。利用通用定时器T1的周期中断事件来启动AD转换-DSP2407, the AD conversion process.
cntrlr
- verilog code for bus controller
softUartRxd
- 单片机软件模 串口接收 用普通io口-uart rxd
EIDORS-simple-3D-fwd_model-structure
- EIDORS简单3 d fwd_model结构-EIDORS simple 3D fwd_model structure