资源列表
dcmbmp
- 在内存中将dcm转化成bmp,然后显示。是一段在软件中实际应用的代码。
drawcirclewindows
- windows下的绘图程序，画圆-windows of mapping procedures Circle
ledcontrol
- FPGA驱动LED静态显示 --文件名：ledcontrol.vhd --功能：译码输出模块，LED为共阳接法 -FPGA-driven LED static display- File Name: ledcontrol.vhd- Function: decode the output module, LED is connected in a total of Yang
4step2iirfilter
- 用VerilogHDL实现一个阶数为4，两个支路的并行IIR滤波器，可以用同样的方法实现更多支路的滤波器。-With VerilogHDL order to achieve a 4, the two branches of the parallel IIR filter, the method can achieve more with the same branch of the filter.
pcm_slv_top
- 实现了verilog语言的pcm编码功能-verilog pcm module
chengxu
- 60秒倒计时，电子时钟，温度自动控制，可根据温度高低自动报警等；-60-second countdown, electronic clock, automatic temperature control, according to high and low temperature alarm, etc.
Modulator70
- 个人参与的某国家工程并行排序MATLAB程序，用于FPGA的RTLAB仿真，使用Simulink工具生成HDL代码。测试可用。-Individuals involved in sort of a national engineering parallel MATLAB programs for the FPGA RTLAB simulation, using the Simulink tool to generate HDL code. Test available.
DIV_5
- 该源码包包含一个奇分频分频器的Verilog代码及其测试代码。奇分频在许多分频电路中都会用到。-The source code package contains a surprising frequency divider in Verilog code and test code. Odd number of points in the frequency divider circuit will be used in.
SEG
- 采用DE2 实现数码管递增 VERILOG-Using DE2 achieve the digital pipe incremental VERILOG
ReadFaces
- 这个是人脸识别技术模式识别技术，这个时候功能函数模块，主函数另一个文件-zhege shi renlian shibie jishu zhege gongn hanshu mokuai zhu hanshu lingyige wejian
wgsph_lab
- DDFS Verilog DDFS Verilog DDFS Verilog DDFS Verilog -DDFS Verilog DDFS Verilog DDFS Verilog DDFS Verilog DDFS VerilogDDFS VerilogDDFS Verilog
buffer
- ArcGIS FOR Flex API 缓冲区分析-Buffer analysis