资源列表
qvgatiming
- QVGA的Timing verilog 描述
usart.rar
- USART coded in VHDL. It is writted in 5 files. I am uploading the files in order. ,USART coded in VHDL. It is writted in 5 files. I am uploading the files in order.
cc_encode
- 卷积码，并行编码，FPGA，通过了测试验证-CC Code， Parallel Coding， FPGA
ADset
- AD9222接收指令逻辑。（Verilog语言）-AD9222 to receive instruction logic. (Verilog language)
Freq_kx11
- 用51单片机的定时计数器0脉冲进行计数，并用LCD1602显示，如果脉冲特性好，精度可以达到1Hz，带宽1Hz-50KHz（系统时钟12M）-With 51 SCM timing counter pulse count, and 0 LCD1602 shows that if the pulse, precision can reach 1Hz, 1Hz bandwidth 50KHz- 12M clock (system).
1602A-VHDL
- --利用FPGA驱动LCD显示中文字符"年"的VHDL程序。 --文件名 ：lcd1602.vhd。 --功能 ： FGAD驱动LCD显示中文字符"年"。-- Using FPGA-driven LCD display Chinese characters " year" VHDL program.- File Name: lcd1602.vhd.- Function: FGAD drive LCD display Chinese characters " ye
i2cSlave_1
- This the first file that describes an i2CSlave interface.-This is the first file that describes an i2CSlave interface.
music-64
- MEGA64播放音乐功能，注意设置好时序，值得学习-The MEGA64 play music, pay attention to set timing, it is worth learning
PWMPECT
- 一个飞思卡尔的PWM波形学习资料，还有ect模块的学习。-The PWM waveform a Freescale learning materials, as well as the ect module of learning.
int
- 对TIMER中断的处理，MEGE128TIMER中断处理程序，实现定时操作。-TIMER INT
Serial
- Serial.h serial Lione configuration Example from Keil development Installation
FJ8030_fpga.out
- 一种关于FPGA系统设计的时钟约束文件，可以直接添加到主模块以减少Unconstraint path-A timing constraints on FPGA system design documents