资源列表
draw
- 用c++编写的简单绘图程序。供c++初学者学习使用。
squareroot.rar
- vhdl源代码,可以开16比特的平方根，算法简单，速度快,this is a vhdl code for square root
Audio_In_Deserializer
- The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1 Boards and provides an interface for audio input and outpu
vhdl-dianziwannianli
- 基于FPGA的电子万年历，此电子万年历系统主要有8个模块分别设计1. 主控制模块 maincontrol 2. 时间及其设置模块 timepiece_main 3. 时间显示动态位选模块 time_disp_select 4. 显示模块 disp_data_mux 5. 秒表模块 stopwatch 6. 日期显示与设置模块 date_main 7. 闹钟模块 alarmclock 8. 分频模块 fdiv -FPGA-based electronic calen
replace-text
- 自己写的lsp 替换文字,在cad中用查找并替换目标文字-lisp
shumaguan
- 数码管显示八段数字或字符,嵌入式操作系统-Embedded operating system, digital display
VIRTEX2-ISE-VHDL
- XILINX virtex5 板子上做演化硬件时ISE 12.1中的硬件构架语言描述-XILINX virtex5 VHDL
main
- 在windows上使用GTK产生窗口，并用cairo绘制文字并在窗口中显示文字，另让文字产生缩放和渐变的特效。-Generated on windows using GTK window and use cairo to draw text and display text in a window, and the other to produce the text scaling and gradient effects.
gprs
- gprs程序：单向传输调试成功的例程代码，对于不足之处，还未实现gprs的双向传输-gprs technology
New-folder
- different method to implement decoder and on for detectorn
fir25
- 用VDHL写的25阶对称FIR滤波器，在塞克隆3FPGA下验证没有问题（AD采样时钟50Mhz，这个对硬件设计有点要求），里面调用官方乘法器API，要节省资源可以采用CSD编码转换乘法器，可以减少一半以上的资源-VDHL written by a 25th order symmetric FIR filter in Seke Long 3FPGA under verify that no problem (AD sampling clock 50Mhz, this design is a bit
FLASH_WRITE_of_MSP430
- This program first erases flash seg C, then it increments all values in seg C, then it erases seg D, then copies seg C to seg D. Seg C @ 1040h Seg D @ 1000h The EEI bit is set for the Flash Erase Cycles. This does allow the Timer_A Interrupt