资源列表
fir_finall
- 用verilog编写的fir滤波器程序，开发环境可以用ise quartus或active hdl等-verilog prepared with the fir filter process development environment can be used ise quartus or other active hdl
detect
- 一个序列检测器的设计。程序不是问题，关键是理解状态机的编程思想。
single
- verilog 我自己写得按单脉冲发生器，通过了综合和仿真，和频率可变的正弦波发生器，
Desktop
- VHDL code for 16 byte ROM & n bit comparator & a full adder
3valuestest
- code for 3 axis cnc. using 8051 p1=input p2 output
lcdSync-1v0---Fully-functional-
- Quartus II SOPC lcd sync component with avalon streaming sink interface
Speed_Loop
- 永磁同步电机的速度环代码，用于速度环控制。-Permanent magnet synchronous motor speed loop code for the speed-loop control.
state_machine
- 状态机控制步进电机,Quartus II VHDL设计语言-The state machine control stepping motor, Quartus II VHDL design language
motor
- 本程序用于测试4相步进电机常规驱动 使用1-2相励磁 1-2相激励功率增倍，步进角度减半，抖动减少 顺序如下 a-ab-b-bc-c-cd-d-da 又称4相8拍-1-2 phase excitation power double stepping angle halved, jitter reduction The following sequence of a-ab-b-bc-c-cd-d-da is also called the 4 phase 8 beat
key
- 矩阵键盘的DSP28335，CCS调试成功，附加Ｈ文件即可在其他函数中调用。IO口可以采用38译码器，减少资源浪费。-Matrix keyboard DSP28335, CCS debugging success, additional H file can call in other functions. IO port 38 decoder can be used to reduce the waste of resources.
lcdpattern
- Programming on How to configure and use custom characters in LCD
debug-scripts-request
- State to check that the listener code was invoked and that no exceptions.