资源列表
COUNTER
- 对外部输入的高频脉冲信号进行分频，应用于FPGA/CPLD .-External input of high-frequency pulse signal frequency, applies to FPGA/CPLD.
key_scan
- verilog 键盘扫描,数码管显示程序，没有加消抖-verilog keyboard scanning, digital tube display program, there is no increase in consumer Buffeting
UniversalRegister
- 普通的缓冲器 这种设计是一个普通的缓冲器，可以做一个直接的缓冲器，也可以做一个双向的转移缓冲器，还可以做一个递增的计数器和递减计数器-Universal Register This design is a universal register which can be used as a straightforward storage register, a bi-directional shift register, an up counter and a down counter.
lcd
- 这是一个128*64带字库的显示程序，程序只须简单的调用一个显示位置选择函数和一个显示字符串函数就能非常容易的显示汉字。-This is a font 128* 64 with the display program, the program calls a simple choice of the location of a display function and a display string function can be very easy to display Chinese ch
maibo
- 一个基于51单片机的脉搏测定仪的源代码 需要的请下载-jiyu51danpianjidemaibocedingyi
MEGA128ADC
- 采用MEGA128内部AD转换器采集数据，兵通过LED数码管显示出来，是学习 MEGA128的好例子-MEGA128 internal AD converter using the data collected, soldiers come through the LED digital display, is a good example of learning MEGA128
T5.zip
- 能够通过2 位七段数码管显示按键编号，显示范围0‐15 按键采用4*4 方式的矩阵键盘，编号K0 – K15 能够分别统计按键被按下的次数，并通过1 位七段数码管显示，显示范围0‐9 ,Through two seven-segment LED display button number, range 0-15 key way 4* 4 matrix keyboard Number K0- K15 respectively Statistics button is pressed, the
randomization
- 伪随机序列应用设计:利用verilog代码实现伪随机信号的产生-Pseudo-random sequence application design: the use of pseudo-random signals verilog code generation
key_led
- 基于xilinxFPGA测试通过，按键消抖动，verilog编写，控制流水灯-Based xilinxFPGA test, the key jitter elimination, verilog prepared to control water lights
iis_m_2
- iis主模块，实现并行数据转成串行数据和音频数据传输的功能。-iis main module, parallel data to serial data transfer and audio data transmission capabilities.
TLC
- Vhdl code for traffic light controller
sin_cos_module
- Verilog实现的cordic算法的计算sin，cos值得模块，使用rom，代码简洁有效。-Verilog implementation of the cordic algorithm of computing the sine and cosine worth module, use of ROM, the code is concise and effective.