资源列表
FIR_1
- FIR滤波器的verilog实现，实现6级流水线的程序设计。-FIR filter Verilog, has implemented six lines of program design.
FIR_filter_DA_machine
- 用verilog 代码编写的179阶FIR数字滤波器，采用分布式算法实现-verilog code used to prepare the 179 band FIR digital filters, using Distributed Algorithms
bujindianji
- 这是汇编语言，用VHDL语言编的步进电机程序
2-4
- 2-4译码器 -2-4 decoder
time_stamp
- 基于sopc ep2c5开发板的时间标记服务例程-Sopc ep2c5 development board based on the time-stamping services routines
paobiao
- 基于stc89c51 的单片机的跑表设计，计时准确，带有防偷跑功能。-Microcontroller-based stc89c51 the stopwatch design, timing accuracy, with anti-Unleashed features.
50MSeparatefrequencydevice
- vhdl语言设计中常用到的50M分频器，可以以此设计出各种需要的分频器。-vhdl language commonly used in design to the 50M divider, can also be used to design the divider needs.
ADC0
- 基于c8051f020的ADC0转换程序，实现模拟信号的采集-Based on c8051f020 the ADC0 conversion process, analog signal acquisition
Source-Code-PR5
- simple program for the line follower with using PIC 16f690
dac7621
- dac7621数模转换驱动，使用verilog语言写的。-dac7621 digital to analog conversion drive
syn_fifo
- 同步FIFO源代码，使用Verilog编写，用户可以轻松转换成VHDL。-Synchronized FIFO source code
rcvr
- verilog的串口接收程序，有详细注释，适合学习-verilog serial port to receive the program, there are detailed notes, suitable for learning