资源列表
ClockOut
- 通过VERILOG编程，实现FPGA任意整数分频的源代码-through verilog programming, FPGA arbitrary integer frequency of the source code
keyscan_test
- 针对机械式按键存在的抖动问题，用verilog HDL编写了一个采用防抖方案并对按键次数计数的模块，已经在ISE综合通过！-Keys exist for mechanical jitter, with verilog HDL prepared a program with anti-shake button and count the number of modules have been integrated by ISE!
sipo
- Serial In Parallel Out Shift Register in VHDL in Modelsim
LTC1407A
- LTC1407A仿真 可以模拟其全部功能 具有单端输入 时钟 串行输出-LTC1407A simulation can simulate all the functions in its single-ended input clock serial output
Practical-Quiz-4
- ssd1 full ansers from icarnegie
TAXI
- 基于VHDL的出租车计费器，通过VHDL语言来编程实现计费系统的四个功能块：分频模块，控制模块，计量模块和译码显示模块，最后使用MAX+PLUSII软件来对程序进行仿真，以模拟实现出租车的启动，停止以及等待等过程中的计时，计程和计费功能。-Taxi meter based on VHDL, VHDL language programming through the billing system of the four functional blocks: frequency module, co
Ds302
- DS1302实时时钟 时间可调-DS1302 real time clock time is adjustable
PWM
- PWM输出,用PWM方式产生可控制点空比的方波。。可用来驱动步进电机等。-PWM OUT
liushiudeng2
- 基于对51单片机上对灯的控制，用于初学者学习嵌入式单片机。-Based on the control of the lights on the 51, for beginners to learn embedded microcontroller.
decode
- 通信数据中FM0数据的解码接收，解码数据和输出同步时钟。Verilog HDL-FM0 decoding the received data in the communication data, the decoded data and outputs sync clock。Verilog HDL
1602andDS1302
- proteus仿真：1602液晶显示的DS1302实时时钟，单片机采用at89c51，开发语言为c-proteus simulation: 1602 LCD s DS1302 real-time clock, the microcontroller used at89c51, develop language c
LCD1602-4line
- 液晶1604四线制通信，节省IO口，使用更简单。-LCD 1604 four-wire communication, save IO ports, easier to use.