资源列表
divid5_VERILOG
- VERILOG实现无分频时钟，包括测试文件，经过验证可用-VERILOG is no difference between the frequency of the clock implementation, including test papers, can be used after authentication
rc4
- a sample rc4 implementation
wjl99_oth
- 解析字符串，能够从生物信息网站进行字符串的匹配与解析-parsed text for biolog information
3
- 任意十进制转换为2进制，4进制，8进制，16进制-Arbitrary binary decimal conversion of 2, 4 hex, 8 decimal, 16 hex
pinlvji
- 能够较准确的测量1到65535之间的频率，希望对大家有所帮助-To a more accurate measurement of the frequency of between 1 to 65535, we want to help
cjcxcx
- 成绩查询系统，方便在输入成绩后建立表的形式，立于查询成绩，方便，快速。-the system of searching grade
singleton
- 单体的源代码。包括单体的创建，销毁，和使用等。-Create a single body of the source code, very common one. Including monomer to create and use.
1
- 第三届蓝桥杯假设有两种微生物 X 和 Y -3rd Blue Bridge Cup
compile2
- 把两个类似的文件合并，代码为m文件，文件预设24个工况下的文件。-compile two files
zl
- 对主元分析方法的编程，实现降维的目的，并有效的得到得分矩阵，输出结果-Principal component analysis method for programming, achieve the purpose of dimension reduction and effective to get the score matrix, the output
Interphase_Dynamic_Menus
- orcad pcb skill menu
maxsnr
- 相控阵波束形成仿真程序，该程序使用最大噪声的方法对加权函数进行优化-Phased array beam forming simulation program, the program uses the method of maximum noise weighting function to optimize