资源列表
Paralleladder
- 并行加法器VHDL代码，可实现五位加法运算-VHDL code parallel adder
sin_generator
- Sin Generator. 16 points on period.
32bitshiftregister
- 32位带锁存移位寄存器,采用verilog HDL语言编写，可用于串并转换-32-bit shift register with latches, using verilog HDL language can be used for string and convert
VerilogCode_8-bit_2to1_mux
- Verilog Code for 8 to 1 multiplexer for the code to be implemented on Altera DE2 board
ps2_key
- 这是PS2键盘解码试验，在EPM240开发板上验证过的-This is a PS2 keyboard decoder test, the development board verified EPM240
add_tree_mult
- verilog HDL编写的8位乘法器，谢谢使用-the preparation of 8-bit multiplier verilog
kalman_fai
- 信号处理，卡尔曼滤波，一个小程序希望有用哦-Kalman filtering
cx
- 变模可逆计数器的VHDL功能描述，是数字锁相环的一个期间的程序-Reversible counter variable mode
stream_to_asc
- 将二进制码流转换为ASICII文件,可做fpga码表-from bianry streams to ASICII
LPLFSR
- LPLFSR for low power pattern generation.
produce_data
- 用于目标跟踪的数据随机生成大量的数据的基于随机的原则-Used for the data of target tracking random generation of large amount of data Based on the principle of random
LCD-screen-read-data-
- 基于51单片机和12864液晶显示屏读取显示的数据并显示读出的数据-Based on 51 MCU and LCD screen to display the data read and display the data read out of the