资源列表
shuzimiaobiao
- 用verilog实现了一个数字秒表的设计-verilog achieved using a digital stopwatch Design
VHDL05
- ALU算术逻辑运算模块设计代码。内容简单。是个不错的代码，学习的人可以下载参阅。-ALU arithmetic logic operations module design code. Simple. Is not a bad code, people can download the study refer to.
Marquee-VHDL
- 一个用硬件描述语言VHDL进行编写的跑马灯程序，通过改动数据可控只灯亮的顺序-A hardware descr iption language VHDL program for the preparation of the marquee, change the data controlled by the order of only light
Main
- 8051红外接收程序,38K红外接收一体头的程序-8051 IR Receive Program
maq
- Machine declaration in vhdl. It s a very importat project.
Single-chip-digital-clock-
- 单片机实现数字时钟功能，即一个60计数器-Single-chip digital clock function, ie a 60 counter
Train_7
- 在数据段中以buffer单元开始连续存放10个8位二进制无符号数，将其按由大到小的顺序排列-in data segment
pwm
- STC2025写得LED驱动电源PWM调光程序-STC2025 written PWM dimming LED driver power supply program
traffic-light
- 该交通信号灯控制器用于控制一条主干道与一条乡村公路的交叉口的交通(如图8-1所示)，它必须具有下面的功能；由于主干道上来往的车辆较多，因此控制主干道的交通信号灯具有最高优先级，在默认情况下，主干道的绿灯点亮；乡村公路间断性地有车经过，有车来时乡村公路的交通灯必须变为绿灯，只需维持一段足够的时间，以便让车通过。只要乡村公路上不再有车辆，那么乡村公路上的绿灯马上变为黄灯，然后变为红灯；同时，主干道上的绿灯重新点亮；一传感器用于监视乡村公路上是否有车等待，它向控制器输入信号X；如果X=1，则表示有车等
cache
- 使用Verilog实现对cache命中判断的模拟-Use Verilog to realize the simulation of the cache hit judgment
dianzhengxianshichengxu
- 51单片机开发板点阵的显示小程序。需要连接上J16这个跳线帽。这个代码在点阵上显示相应的图形-51 MCU development board dot matrix display applet. We need to connect the jumper on J16. This code displays corresponding graphics on dot matrix
SNAKE100
- a combination of snake and maze program that whenever it hits the asterisk it will post a message ouch . once it reach the point or destination at the end it will move to the next stage-a combination of snake and maze program that whenever it hits th