资源列表
fp_2
- 通过Verilog HDL编程，在CPLD上实现任意小数（分数）分频，分频系数为N+A/B.-By Verilog HDL programming, to achieve any decimal in the CPLD (score) frequency, frequency coefficient N+ A/B.
div_1p5
- 时钟1.5分频的Verilog代码，简明扼要！-Clock frequency of 1.5 Verilog code, clear and concise!
fileread
- file_read vhdl code provide by my teacher for reading file into FSM-file_read vhdl code
heat-sink-design-guid
- intel chip design guide heat sink
che
- 智能小车寻迹控制程序！！！！何飞飞独家设计！-Smart car tracing control program! ! ! ! He Feifei exclusive design!
blink.c
- Simple AVR Test program. Blinking LED.
Sinusoidal
- sine generator in rom with 512 points.
bsp_circle_patch
- planar code for frequency selective surface, which could predict the resonace freq of the circle patch frequency selective surface
CCSCANA
- CAN bus communication example 3-CAN bus example 3
ad0809
- ad0809状态机样例，使用多状态机方式，有六个状态-ad0809 sample state machine, using a multi-state machine has six state
cic-dicemator
- 该文件包含数字抽取滤波器cic的verilog代码，经测试可用，且简介，消耗硬件资源较少。-This file contains digital sampling filter cic verilog code, after testing is available, and the introduction, less consumption of hardware resources.
CRC校验单片机C源码
- CRC校验单片机C源码，供MODBUS程序使用