资源列表
Debouncer_Ver2
- super fast debounce button on vhdl, xilinx xc
ca60
- 60分频器，将主频分频，产生系统所需信号。-60 divider, the frequency divider to generate the necessary signal system.
KBD
- key setting for chipcon 2530
servo.c
- rotates servo using pic 18f4520
shift_reg
- Shift reg in vhdl, a first example to start
N_Bit_CLA_4.0.vhd
- N-Bit Carry Look Ahead adder
2
- 使用变量的状态机 library ieee use ieee.std_logic_1164.all ENTITY fsm2 IS PORT(clock,x : IN BIT z : OUT BIT) END fsm2 ------------------------------------------------- ARCHITECTURE using_wait OF fsm2 IS TYPE state_type IS (s0,s1,
pri_encoder_using_if.v
- this is a verilog source code for priority encoder using if statement.
main
- AT芯片 部分主函数，仅供参考 动力电或照明电测量-AT chip code
virtex5-C
- 使用FPGA VIRTEX5 板子做演化硬件时SDK平台中C语言描述。-FPGA VIRTEX5 C
HDQ
- 用于TI电池管理芯片的通讯，HDQ头文件-For communication TI battery management chip, HDQ header files
ieee-to-unsigned
- IEEE32转unsigned 代码，在单片机上实现，很实用小程序-Turn IEEE32 unsigned code, on the single chip microcomputer implementation, very useful small program